PhD Defence Ghazanfar Ali | Embedded Test Instrument for Aging aAware Multi-Processor System-on-Chips

Embedded Test Instrument for Aging aAware Multi-Processor System-on-Chips

Ghazanfar Ali is a PhD student in the department Computer Architecture Design and Test for Embedded Systems. (Co)Promotors are dr.ir. M. Ottavi and dr.ir. N. Alachiotis from the faculty of Electrical Engineering, Mathematics and Computer Science.

As Complementary Metal-Oxide-Semiconductor (CMOS) technology advances, integrated circuits (or chips) are becoming increasingly complex and powerful. These chips are widely employed in automotive, aerospace, industrial control, and medical equipment. Reliability is paramount in such safety-critical applications, as even minor failures can lead to serious consequences. However, the increased complexity of modern chips also accelerates ageing, resulting in performance degradation over time.

This thesis focuses on enhancing the long-term reliability of these systems by integrating specialized on-chip sensors known as Embedded Test Instruments (ETIs). These ETIs continuously monitor the chip’s behaviour, assessing critical parameters such as operating speed, power dissipation, and temperature. Monitoring these factors enables early detection of wear and degradation, allowing for timely intervention before failures occur. A central contribution of this work is the development of a methodology to ensure that ETIs are both reliable and highly correlatable. The proposed ETIs can accurately measure slack time in critical paths, detect variations in supply current, monitor voltage droop due to switching activity, and sense on-chip temperature fluctuations. The designs were implemented and evaluated using 40nm CMOS technology, demonstrating high accuracy and efficiency.

Moreover, this research illustrates the application of these correlatable ETIs in two key areas: end-of-life (EOL) prediction and hardware security. For lifetime prediction, a data fusion methodology based on principal component analysis (PCA) aggregates multiple ETI outputs to improve the forecasting of degradation in critical circuit components. For hardware security, a system-level methodology shows how voltage-droop and temperature ETIs can enhance the stability of Physical Unclonable Functions (PUFs).

Overall, this work contributes to the development of more dependable electronic systems through on-chip monitoring, promoting enhanced reliability and security