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PhD Defence Gijs van der Bent

stacked fet based gaas monolithic microwave high power amplifiers for active electronically scanned array radar front-ends

Gijs van der Bent is a PhD student in the Integrated Circuit Design group. His supervisor is F.E. van Vliet from the faculty of Electrical Engineering, Mathematics and Computer Science. 

The High Power Amplifier (HPA) is a key component for any modern Active Electronically Scanned Array (AESA) radar front-end, both in terms of costs and performance. The task of this HPA is to generate the high level of required output power with an efficiency that results in feasible requirements for the cooling of the system. This must be combined with a reasonable cost price and reliable operation.

To increase the supply voltage of a radar front-end yields several advantages. At the system level, lower DC currents are present, resulting in lower losses in the supply lines. On transistor level, the real part of the optimum load impedance is higher, which eases the matching problem, resulting in matching networks with higher bandwidth or lower loss. State of the art technologies based on wide-bandgap materials such as GaN, support the requirements for high supply voltages. The cost of these technologies, however, is significantly higher than the GaAs technologies, while the latter still have a more proven record of reliability.

The research question addressed in this thesis is whether the advantages of an increased supply voltage can be obtained without the use of a wide-bandgap semiconductor technology, specifically by the application of the Stacked-FET technique. At the heart of this approach is a single Common Source (CS) FET, followed by one or more Degenerated Common Gate (DCG) FETs. Stacking a number of transistors linearly increases the overall breakdown voltage and hence the possible drain supply voltage, providing the previously mentioned advantages. An additional benefit of the Stacked-FET concept is due to the internal power combining by voltage summation, which decreases the chip the area required for passive combining networks.

Answering this question is not a straightforward matter. The voltages and currents of the individual transistors in the Stacked-FET should be well balanced in order to efficiently combine the RF power contributions of these transistors. The Stacked-FET should operate without any instabilities, which is not trivial due to the presence of the DCG FETs, which are inherently unstable. Balancing and stability are not always compatible and the goal of the design is to find the solution which yields a Stacked-FET configuration with maximum RF performance within the boundary condition of stable operation. Stability needs to be ensured by design, as unstable operation may instantly lead to failure. Finally, the simulation of power transistors operating at microwave frequencies requires transistor models that accurately describe the intrinsic and parasitic effects, not only in the operating frequency band but, due to the requirement of accurate prediction of instabilities, for the entire frequency range from DC to the maximum frequency where the transistor exhibits gain. This research question has been addressed by others, for example at lower frequencies, at low power levels or including numerous simplifications. The aim of this work is to answer this question for contemporary S-Band high power amplifiers and without simplifications that might unnecessarily limit achievable performance.

The reported results demonstrate that GaAs Stacked-FET power amplifiers, designed according to the strategy defined in this thesis, can deliver an output power in excess of 25 W with a PAE higher than 40 % over a bandwidth of 30 % at S-band frequencies. With this RF performance, these devices can be competitive to many GaN based amplifiers, at significantly lower costs.