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Ultra Low Power Data Converters Design Techniques in 28mm FDSOI

Project Number:
Project Manager: Prof. dr.ir. Bram Nauta
Faculty of Electrical Engineering, Mathematics and Computer Science
Tel.: +31-53-4892655
Email: b.nauta@utwente.nl 


In the future we will be equipped with tons of wireless devices around us, which collect some form of useful data for us. These devices collect data via sensors and preferably transmit them in a wireless way. Already back in 2007 the Wireless World Research Forum (WWRF) [1] predicted that there would be 1000 wireless devices per person on average in 2017. Since we do not like to charge or replace 1000 batteries per day or even per month, we need to reconsider the energy use of the electronics behind it.

One of the key enabling electronic circuits is the analog to digital converter, which converts the information of the sensor to the digital domain. Once in the digital domain, the power can be extremely low, as long as the computational effort is low. Just like in wristwatch where the battery last for a few years.

In the recent past a revolution in AD Converter Land has been initiated by the work of [2] (A 10-bit Charge-Redistribution ADC Consuming 1.9 μW at 1 MS/s, presented at ISSCC in February 2008) where a Successive Approximation (SA) AD Converter was presented which consumed 20 times less power than state of the art at that time. It then took until mid 2012 until other researchers were able to get to this low level of power consumption [4]. This work has clearly set a trend and now every respected conference has a dedicated session on SAR ADCs.

The work in [2] uses many innovative ideas and one of them is that the converter has no static power consumption as well as no bias. It operates as if it were a digital circuit: it only consumes charge from the supply when it’s used on an active clock. If there is no clock there is no energy consumption at all.

General block diagram of a SAR ADC.

Ultra Low Power Data Converters Design Techniques in 28nm FDSOI


Performance of [2], uses the SoA data base in [5]

There are many challenges left in this field: Can we make more than 10 bits, as the linearity clearly becomes a bottle neck for the architecture used, can we save a factor 100 in power consumption since digital power consumption also scales down with shrinking technology nodes? Can we make absolute accuracy? In a use case such as ultra low power autonomous wireless sensor node, can we use the energy coming from the input signal issued from the sensor to supply the ADC?

STMicroelectronics has decided to continue for the next technology nodes on a planar process basis. The technology nodes to be considered in this thesis are 28nm and 14nm CMOS. 

The Planar UTBB FDSOI technology is the best fitted solution to address the challenges of energy-efficiency for complex wireless Digital Products, from 28nm down to 10nm. UTBB FDSOI technology, in combination with body biasing, enables a significant performance boost and power reduction over standard bulk CMOS process. The performance boost at low voltage is even larger, dramatically improving energy efficiency for low-end use cases hence battery life time.

Ultra Low Power Data Converters Design Techniques in 28nm FDSOI 

The goal is to investigate the out of the box advantages that draw from the FDSOI process and the use case is an extremely low power ADC which has to improve by one or two orders of magnitude the existing state of the art in energy efficiency. Novel analog design techniques drawing directly from a smart usage of the body tie of the planar transistors will be extensively investigated.

The knowledge drawn from this project will bring up new design ideas to be used later in high speed data converters in this technology.

The final goal of this work is to set a new benchmark for low power and develop new architectures to enable sustainable operation of ultra low power sensor networks.

Project duration: 1-7-2014 / 1-7-2018
Project budget: 70 k-€ funding
Participants: STMicroelectronics Crolles, ISEN/IEMN Lille, UT
Project budget CTIT: k-€ / k-€ funding
Involved groups: Integrated Circuit Design
CTIT Research Centre: Centre for Array Technology