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BASTION: Board and SoC Test Instrumentation for Ageing and No Failure Found

Project Number: 619871

Project Manager: Dr.ir. Hans G. Kerkhoff

Faculty of Electrical Engineering, Mathematics and Computer Science

Tel.: +31-53-4892646

Email: h.g.kerkhoff@utwente.nl

Project website: BASTION


It is widely and well understood that shrinking feature sizes in semiconductor manufacturing technologies keep causing new reliability issues – especially in consumer electronics. The 2012 ITRS lists ageing (NBTI, PBTI, HCI, etc.) in semiconductor devices as one of the few most difficult challenges of process integration that affects reliability. Another hard issue is product-level malfunctions that are difficult or impossible to reproduce – referred to as No Failure FoundNFF (also known as No Trouble Found – NTF).

Due to electrochemical effects, the ageing rate is a function of feature size that tends to increase when shifting to new technology nodes. Being almost unnoticed by today’s user, ageing will eventually manifest itself clearly by the end of the current decade. NFF in its turn is caused by a combination of test escapes, ageing, and environmental impact. The lack of understanding failure mechanisms and need for modelling new materials processes and devices are both constantly increasing. Hence, the impact of both phenomena is expected to grow unless corrective actions are taken.

NFF is being increasingly reported by industry and according to Accenture Report, in 2008 in US, around 70% of all product returns were characterized as NFF. Cost-wise (including returns processing, scrap and liquidation), NFF amounted up to 50% of total 13.8 billion USD (10.5 billion EUR) returns and repairs cost in US, which approximates to 25 USD (19 EUR) per year per capita.

The figure below illustrates how these main focus points are connected together in BASTION and addressed in corresponded work packages. A consortium of eight companies and universities will tackle these issues, starting from January 1st 2014.

Project duration: 1 January 2014 – 31 December 2016

Project budget: 4.65 M-€ / 3 M-€ funding

Number of person/months: 436 person months

Project Coordinator: TESTONICA Lab

Participants: TESTONICA, Tallinn University of Technology, ASTER Technologies, Lund University, Politecnico di Torino, University of Twente, Hochschule Hamm-Lippstadt, Infineon

Project budget CTIT: 658 k-€ / 515 k-€ funding

Number of person/years CTIT: fte/year

Involved groups: Computer Architecture for Embedded Systems (CAES)

CTIT Research Centre: Centre for Array Technology