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Places2Be: Pilot Lines for Advanced CMOS Enhanced by SOI in 2x nodes, Built in Europe

Project Number: 325633

Project Manager UT: Prof. dr. ir. Bram Nauta

Faculty of Electrical Engineering, Mathematics and Computer Science

Tel.: +31-53-4892655

Email: b.nauta@utwente.nl

Project website:


The general goal of this project is the industrialization of 28/20nm Fully Depleted (FD) Silicon On Insulator (SOI) Technology platforms, enabling 2 different sources in 2 different European countries. The project also aims at establishing and reinforcing a design ecosystem in Europe using these platforms. Last, the project considers extremely important to explore extension towards FD devices at 14/10nm, in order to continue the road toward more efficient technologies.


PLACES2BE aims at introducing a FDSOI technology for the first time in mainstream digital CMOS for consumer applications, in the Internet multimedia communication field and other applications requiring highly energy efficient digital electronics, such as mixed signal applications addressing the whole range of future societal needs such as safety, health and well being, energy. PLACES2BE will also exploit the capabilities of the FDSOI advanced CMOS technologies for RF and AMS designs.



This project will achieve the following breakthroughs:


First 28 nm and then 20 nm FDSOI capacity installed in the World.


First 20 nm CMOS capacity installed in Europe


Offer of wide dynamic range with the most energy efficient technologies: able to address both low power and high performance applications.


The 28 nm (resp 20 nm) FDSOI technology should be able to offer 20% performance (speed) improvement over its bulk counterpart at nominal voltage, a wider voltage range operation around 0.4 to 1.2 V with up to a 10x speed boost at 0.4V, as well as a greatly enhanced energy efficiency from 20% in the high range of operating voltage to a factor of 2.5 (-60%) in the lower range of operating voltage.


Offer the capability to dynamically adjust the devices performance / power trade-off thanks to the back biasing feature

Project duration: 1 February 2013 – 1 February 2017

Project budget: 358.8 M-€ / 52.6 M-€ funding

Number of fte’s: 500 fte

Project Coordinator: STMicroelectronics

Participants: STMicroelectronics SA, STMicroelectronics SAS Grenoble, ST-Ericsson SAS, Commissariat à l'énergie atomique et aux énergies alternatives, SOITEC SA, Adixen Vacuum Products, Mentor Graphics, Ion Beam Services, Institut Polytechnique de Grenoble, Dolphin, Université Catholique de Louvain, IMEC, ST-Ericsson Oy, GlobalFoundries, Forschungzentrum Jülich, University of Twente, Axiom, Bruco Integrated Circuits, eSilicon, ACREO, ST-Ericsson (Lund), Ericsson AB

Project budget CTIT: 930.8 k-€ / 399.2 k-€ funding

Number of person/months CTIT: 82 person months

Involved groups: Integrated Circuit Design (ICD)

CTIT Research Centre: Centre for Array Technology (CAT)