funded by Essent/Gasterra
Project Manager: Prof dr. ir. Gerard Smit
Faculty of Electrical Engineering, Mathematics and Computer Science - EEMCS
Tel.: +31 53 489 3734
This is a PhD project, funded within the framework of the Essent/Gasterra collaboration agreement. It has a strong connection with the STW-funded project SFEER.
For optimised operation, local and global scheduling algorithms have to be developed. The local scheduling algorithm tries to optimize the operation of the micro-CHP and the thermal store in a certain house. The global scheduling algorithm tries to optimize a fleet of micro-CHP appliances.
Currently, the local scheduling algorithm is a learning algorithm and is solely based on the thermal load pattern of the home related to central heating and hot tap water and the wholesale electricity price (APX). In future scenarios household appliances will get more “intelligent”. These appliances might be able to shift their electricity or hot-water/heat load. For example the washing machine could be programmed that the laundry should be washed between 10:00 and 17:00. The local scheduler could pick the right time for it for example when heat is needed in the house, or the elec-tricity wholesale price is high.
Currently the global scheduling algorithm only takes part of the wholesale market into consideration, namely the day-ahead market (APX) and the demand side of the balancing market, but also other factors can be considered as well for example:
- Instant electricity requests (supply side of the electricity balancing market)
- Operation/balancing of the electricity network: e.g. by controlling the amount of micro-CHP appliances that start / stop / run simultaneously, for example to pro-vide reactive power. If such scheduling can be done efficiently, the provision of reactive power to network operators could become an additional source of reve-nue to the supplier operating the micro-CHP appliances.
Project duration: 2007-2011
Project budget CTIT: 200 k-€
Number of person/years CTIT: 1 fte
Involved groups: Computer Architecture for Embedded Systems (CAES)