CeO2 and HfO2 High-k Gate Dielectrics by Pulsed Laser Deposition: from binary oxides to nanolaminates
Promotion date: 20 April 2006
Electronic devices, we all know, are getting smaller and smaller. The journey of integrated circuits started by a handful of transistors per square centimetre, and now in modern processors, there are hundreds of millions transistors. This is done by the miniaturization of the transistors in devices. By miniaturization of the devices, every component has been scaled down, the gate area of the transistors in particular. Maintaining the high gate capacitance in smaller devices can be done only in two ways. The first one is what has been done since the beginning of semiconductor technology, e.g. decreasing the thickness of the gate oxide. However, the thickness of the state of the art dielectrics (SiO2 and SiON) is approached to sub-nanometer level.
What was your thesis about?
Electronic devices, we all know, are getting smaller and smaller. The journey of integrated circuits started by a handful of transistors per square centimetre, and now in modern processors, there are hundreds of millions transistors. This is done by the miniaturization of the transistors in devices. By miniaturization of the devices, every component has been scaled down, the gate area of the transistors in particular. Maintaining the high gate capacitance in smaller devices can be done only in two ways. The first one is what has been done since the beginning of semiconductor technology, e.g. decreasing the thickness of the gate oxide. However, the thickness of the state of the art dielectrics (SiO2 and SiON) is approached to sub-nanometer level. An insulator with a thickness below 1 nm suffers from a phenomenon called ‘direct tunnelling’, which prevents providing a good electrical isolation between the gate and the channel of the transistor. Therefore, very thin oxide layers are not good enough for the leakage current (current transported between the gate and the channel) requirements for novel devices. The second solution for maintaining the high gate capacitance is using a gate oxide material, which has a higher dielectric constant (k) than conventional materials (SiO2 and SiON). By using a material with a higher dielectric constant, called as high-k gate dielectrics, gate capacitance can be maintained without sacrificing the thickness of the gate dielectric. High dielectric constant allows using thicker oxide layers, and thicker gate dielectrics give better leakage current characteristics. This is the motivation that stands behind the need for high-k gate dielectrics. I have been working on developing a good insulator to be used as gate dielectric; trying to find a new material that will isolate the gate from the channel and meet the gate leakage requirements in smaller transistors for near and mid-term future.
The major problem is the silicon substrate itself. Silicon is the material to use in most of the integrated circuits, which we owe most of the technological development in microelectronics in last decades. Silicon has a great companion, it’s natural oxide: SiO2. Si and SiO2 has performed very well from the early years of integrated circuit technology. However, the above mentioned reasons forces us to break-up this relationship and use a different oxide than SiO2. When you put a different oxide on top of silicon, silicon starts to react almost instantaneously with that material, again resulting in a thin SiO2 layer, which is called as interface oxide. The problem is, this interface oxide layer has the same insufficient dielectric constant. An ideal gate dielectric material has to meet a number of different requirements, among which thermodynamical stability, good electrical properties, production possibilities etc.
I chose hafnium dioxide (HfO2) – the primary choice of industry – combined with cerium dioxide (CeO2). There are several ways to combine these materials, like mixing or depositing them as different layers stacked on each other, called as laminates. In this work, I tried to find out the differences between the laminated structures and the binary (pure HfO2 or CeO2) oxide layers.
So the hot spot in your work was the laminated structures of CeO2 and HfO2?
Yes, that’s true. I’m certainly not the first person who made laminated thin films. But comparing the different aspects of these kinds of layers related to the lamination and individual layer thickness to this extent and benchmarking them with binary oxide layers is a good contribution to high-k dielectrics research. The good thing is I was able to demonstrate the advantage of the laminated structures compared to the binary oxide layers.
So will it soon be used in industry?
Well, I’m not sure about that. The laminated layers provide really promising properties for dielectric applications but seeing them on the production line may require a longer time.
Depositing one layer of binary oxide is certainly much faster than depositing alternating oxide layers in form of laminates in current production technology. For industry, a faster operation is always the cheaper option and we have to wait till the end of the cheaper options for seeing the more expensive solutions in the market. But in the end the laminated layers, also for transistors, are always attractive for manipulating the interfaces, which gradually have greater importance in devices.
What did you like best about your research?
I increased my knowledge a lot. This kind of research allows you to go deep in several different fields; physics, chemistry, material science. Combination of the production of the layers with their structural and electrical characterization gave me the chance to improve myself in a very wide range of skills and knowledge. That, I believe, was a unique advantage of this project. I do not think there are too many people in the world in that field that combined the making from the scratch and the measuring.
Was there something you did not like?
I have nothing to mention something as I didn’t like but of course I had some difficulties during the project, which were not directly related to the project itself. As I said, I was working in a very wide field in this project, which also means that I worked together with people from different fields. Actually this is something I found particularly nice and an enriching experience. However, keeping the communication healthy between all parties of the project, which have different approaches for problem solving, was sometimes challenging.
You are from Turkey?
Yes, I used to live in Istanbul before I came to Enschede. I started a PhD there, at Istanbul Technical University, working in a NATO Science for Peace project in collaboration with University of Twente, with prof. Dave Blank. After three years, my supervisor passed away and I quit my PhD there and started a new one here at University of Twente with Dave, who offered me this position. I immediately recognized the challenge and took the chance.
What will you do next?
I will continue to work with prof. Dave Blank, in Inorganic Materials Science Department, in MicroNed project, which is the sister project of NanoNed programme as a post-doc. I like the working environment here, I got used to all these labs and equipment, and I think, I still have more things to learn and to give here.