MESA+ Institute for Nanotechnology

In this thesis a full-scan test method is introduced that can be used to test handshake circuits. Handshake circuits are a class of asynchronous circuits that are designed according to set of rules that guarantee correct operating circuits. The circuits used in this work are designed using the Tangram toolkit that was developed at Philips Research.

Handshake circuits are more difficult to test than conventional synchronous circuits, because of a number of reasons. Most importantly is the fact that the circuits behave autonomously. Internal operations can occur independently of external input signals, which limits the outside control that can be exerted on the circuit. Other testing problems associated with handshake circuits are the higher number of sequential elements in the circuits, as compared to synchronous circuits, and to a lesser extend problems with initialization and non-deterministic behavior.

For a test method to be cost effective, a number of properties are important. Traditionally minimization of the area overhead has been crucial, but the possibility of offering an automated flow and guaranteeing high fault coverage are also increasingly important. The full-scan test method was chosen because this method offers an automated flow and high fault coverage, even though it requires a higher area overhead.

The full-scan test method modifies every sequential element in the circuit into a scan element. Scan elements have a multiplexer on the data input that can be used to connect all scan elements serially in a shift register. All scan elements are controlled by a global clock signal that is added to the circuit to support the scan test. Clocking is based on a pair of two-phase non-overlapping clock signals, which apart from safe timing also support a transparent mode in which the circuit behaves functionally as an unmodified asynchronous circuit.

Many of the sequential elements used in handshake circuits consist of C-elements. A C-element is a generic form of a set-reset latch. Several different types exist; each with alternative set and reset functions. In total about a dozen variations are commonly used. For use in a scan test method, the C-elements have to be modified into scan testable C-elements. Two modifications are required: the addition of a scan data input and the addition of clock input to control the element. These modifications increase the size of a C-element, which combined with the fact that a typical handshake circuit contains a large number of C-elements will result in a high overall area increase of the circuit. To counteract this, smaller scannable C-elements are designed at transistor level and circuits are optimized to reduce the number of C-elements.

Handshake circuits can also contain conventional latches and flip-flops. These are used in the data path and are clocked with local clock signals generated by a control block. For the scan test method, a global clock has to be multiplexed onto these local clock signals. This is implemented by inserting a common multiplexer in the local clock signal, however, to be able to test the clock multiplexer itself, separate tests are used for the data path and the control block. Each of these two tests will cover a part of the faults in the multiplexer, and together they cover all faults in the multiplexer.

One of the main reasons to choose the full scan test method, is the availability of a large number of existing tools that, without modification, can be used to generate the test patterns. In addition these test tools support hierarchical test generation. This allows the tests for the control block and for the data path to be generated separately first and later combined into a top-level test. During test pattern generation, C-elements and latches are remodelled by flip-flops. This is required to make the test pattern generation tool to recognize them as valid scan elements.

The method has been applied to several benchmark circuits, which were processed fully automatically. The results show that a high fault coverage is achieved, equal to that of a synchronous circuit. The required area overhead is however much larger than that of a scannable synchronous circuit. Using gate-level scan C-element implementations results in an average overhead of around 80%. By using an optimized transistor level library, this reduces to around 35%. To reduce the area further, a number of potential optimizations have been identified.