MESA+ Institute for Nanotechnology

The increasing time-to-market (TTM) pressures have created the demand for rapid design of single complex chips based on reusing the design and test data. On the other hand, the availability of shrinking process technologies makes it possible to integrate a number of digital and analogue functional blocks into a single chip, mixed-signal System-on-a-Chip (SoC). Due to the complexity of a SoC and the limited test access (lack of controllability and observability) for embedded analogue cores in the pin-limited SoC, there are a lot of technical challenges in the testing of embedded analogue cores in SoC.

A hierarchical approach has been employed for testing of embedded analogue cores in our research. In this approach, the test signals for each standalone analogue core in the SoC are selected first. Next, some test translation schemes are employed to translate the core-level test signals into system-level test signals. The research presented in this thesis deals with the system-level testing of embedded analogue cores in SoC, i.e. how to translate the core-level test patterns into system-level.

The main task of the test-translation procedure is to propagate (backward and forward) those core-level test-input signals and test-output responses of each stand-alone core to the primary SoC inputs and outputs. Meanwhile, the corresponding tolerance boxes, which are the result of the allowed process-parameter variations during manufacturing, are also propagated to the primary SoC outputs for setting the corresponding optimal test thresholds. These thresholds are used to determine whether the chip under test is good or faulty during final production testing.

Tolerance-box generation in SoC testing is a very CPU-time consuming procedure with the traditional Monte-Carlo approach. By using the sensitivity analysis technique, this thesis proposes a new fast core-based tolerance-box generation and propagation approach for the testing of embedded analogue cores. In this approach, sensitivity analysis for each stand-alone analogue core is carried out first. Then, by using the proposed propagation algorithm, the tolerance box for the complete test path can be obtained. As the original points in our approach, the concept of the sensitivity is extended to core sensitivity and a new model for different categories of parameter deviations is proposed. The application of this approach to an example circuit shows that the proposed approach is very effective for the tolerance-box generation in the testing of embedded analogue cores.

Test signal backtracing is the procedure to determine a stimulus at the primary SoC inputs that will produce the desired test signal at the inputs of the embedded cores under test. A PID (Proportional Integral Derivative) feedback loop based backtrace method has been proposed in our research. With this proposed method, the test input signal for the embedded core could be backtraced to the primary SoC inputs in the time and frequency domain. Moreover, the computational effort for the backtrace procedure is low since it is quite easy to implement the PID controller in the high-level language during simulation. The presented theoretical analysis, simulation and measurement results show that the test-signals of the embedded cores can successfully be backtraced to the primary SoC inputs.

Analogue fault simulation is a CPU-time consuming procedure. A new general structure for mixed-level modelling with three stages is proposed in this thesis to speed up analogue fault simulation. In this structure, the original transistor-level circuits are reused for the input stage and output stage. The functional stage is an equation-based part to represent the function of the original fault-free block. This structure has been applied to one block of an actual industrial chip. The fault simulations have been carried out using this mixed-level model. The results show that this kind of mixed-level modelling can effectively reduce the fault-simulation time, while providing the same results for fault simulation.

During test translation, some core-level test patterns might not be able to translate to the system-level due to the limited test access of the embedded cores. In order to solve this problem, a mixed-signal P1500-compatible core-based testing architecture is proposed in this thesis. The digital cores with the P1500 test wrapper can be directly used in this architecture to get extra test access because of its good compatibility. The new analogue input and output wrapper cells and analogue test buses have been designed and used to provide test access for the analogue testing of embedded mixed-signal cores. As an example, one analogue test path of a SoC including the new core-based architecture was evaluated by means of simulation. The simulation results show that the performance degradation and silicon area overhead of the extra DfT are acceptable for testing of embedded analogue cores.

Summarising, with the methods proposed in this thesis, the core-level test patterns for embedded analogue cores can be translated into the system-level test patterns. In other words, the research presented in this thesis provides an effective solution to the system-level testing of embedded analogue cores in SoC.