Tailoring Strain in Microelectronic Devices
Promotion date: December 6.
Promotor: Prof.dr. Jurriaan Schmitz
Assistant Promotor: Dr.ir. Rob Hueting
In this thesis an innovative concept is proposed in which the gate of a transistor is controlled over the channel by using mechanical strain. The device used is a fin shaped field effect transistor (FinFET). Here, a typical FinFET is studied from NXP-TSMC Research.
A thin layer of titanium-nitride (TiN) is deposited as a gate at an elevated temperature. When cooled down this material shrinks faster than does the silicon. This compresses the silicon fin, resulting into negative strain.
This strain moves down the silicon conduction band edge. A secondary effect, quantum confinement, is confirmed by measurements as is the strain effect on the leakage current.
It is proposed to clamp the FinFET between two piezoelectric layers. An analytical model and specialized simulations are used to show that the FinFET is capable to move the thermal limit of the ‘subtreshold swing’. This concept is used to describe the reduction of the leakage current and enhancement of the maximum flow of current.
However, the choice of materials and structures for this promising so-called strain modulated FinFET is still not straightforward.
Was your PhD work application oriented?
My PhD research was aimed at tailoring mechanical strain in semiconductors. Along the way we studied various devices where strain plays a major role. For example, nowadays the so-called Tri-Gate or FinFET transistor is introduced by semiconductor companies. We discovered that the leakage current is dependent on the transistor due to thermally induced strain.
A second example involves the so called Bulk Acoustic Wave (BAW) resonators. In these devices the synchronization of electronic and acoustic (strain) signals result in a strongly frequency selective filter. These devices are commonly used in GSMs.
We developed a simple and straightforward method to analyze the non-linear parameters of the piezoelectric, strain inducing materials in these filters. Finally we proposed an upgrade for the FinFET: a piezoelectric layer to strain the transistor as it is turned on. This upgrade increases the current only when it is desired.
All of my research activities mainly focused on measurement, modeling and simulation of the various devices.
In what way did you develop personally, as a scientist and researcher?
I reflect on the results obtained more frequently now, and I put these results into a larger perspective in a much earlier phase of research. This prevents me from being satisfied with partial results too quickly. Also I am looking more for collaboration relations and input from experts in other fields of research. In this way my work gains weight and significance.
Did you manage to have some nice publications along the way?
Last year I had an article published in Applied Physical Letters. This year two were published in IEEE Transactions on Electron Devices.
What are your future plans?
After these years of study and research in academics, I am looking forward to go and work in industry. Now it is more important for me to see the results of my work being used in market products. I am quite sure my modeling and experimental skills are of importance in the semiconductor industry.
Did you feel part of the Mesa+ community during your PhD period?
I didn't have a lot of collaborations within the Mesa+ institute, neither did I use the cleanroom facilities. Instead I collaborated with NXP Semiconductors and the University of Udine. As a result I felt more
connected to them as I did with Mesa+. However, I did enjoy the annual events such as the Mesa+ Days and the Glühwein parties!