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Guido Sasse (promotion date: 4 July 2008)

Reliability engineering in RF CMOS

Promotion date: 4 July 2008

Thesis advisors: prof. dr. Jurriaan Schmitz, prof. dr. ir. F.G. Kuper

New developments are presented for reliability engineering in RF (radio frequencies) CMOS, comprising of three subjects:


A new methodology is described for high-frequency on-wafer experiments. It was investigated whether the degradation of MOS transistors is dependant on the frequency of the voltage signal with which it is stressed. Gate-oxide breakdown has proven to be so. At increasing frequency the lifetime of the device increases. Hot-carrier and NBTI degradation both prove to be frequency independent.


A new simulator is presented that allows for a better prediction of the lifetimeof RF circuits, with special attention to RF power amplifiers. Using the new simulator, the expected lifetime of these circuits is found to increase considerably.


Two measurement techniques are described that can be used for the reliability evaluation of MOS transistors in CMOS technologies: RF C-V and RF CP.

Why is degradation of CMOS circuits an important issue?

This technology is widely used in applications for mobile communication. In high power applications CMOS is not so common yet, due to thin gate-oxide that can break down.

This can be tested, but it is not exactly clear how complete circuits keep performing, when breakdowns take place under specific voltage and frequencies stresses, found in this particular region.

CMOS reliabiaility is a topic of much interest and a lot is known regarding degradation mechanisms in CMOS technology. However, when applied in RF applications, device degradation may possibly not be modelled using present models, which were developped for digital applications. This was the main reason for performing this research: to investigate how applicable these models are.

Did you find some clear results?

I developped two characterization techniques for present-day MOSFETs. These have very thin gate-oxides, thereby prohibiting the use of a couple of conventional MOSFET characterization techniques. It appears that the use of RF measurement techniques is a solution to this problem.

I build a simulator to measure the performance of complete circuits. It was previously known that gate-oxide breakdown is not always desastrous for the performance of RF circuits. Using the new simulator this knowledge can be fully utilized. These practical results are important for future IC-designers.

Apart from these practical results, also a more fundamental physical effect was found. Breakdown of gate-oxide at a given voltage waveform, is dependent of differences in the frequencies of the stress signals. It is the first time that this kind of dependence is measured.

In what way is your research a MESA+ project?

This research contributes to the understanding of nano devices in the near future. First of all, I hope to contribute to the way future designers in the IC industry learn to work with these new insights - the more fundamental as well as the simulator experiences - in designing new devices in a creative manner. I worked closely together with members of the IC-Design group, and my promotors Jurriaan Schmitz and Fred Kuper.

Did you make future plans already?

I found a job at NXP Philips in Nijmegen. The reliabiaility of RF CMOS is a very important topic in my new working environment, as is the use of the simulator and models I studied for the last four years.

I guess in a commercial setting, exact measurements and testability will play a central role. The products involved will be produced in big series, at last. But, all in all, the work there, will not be that different. The engineering side of my work I like very much, I noticed during my research project here. That will be okay, no doubt!

What do you think of the future of MESA+?

MESA+ is a big name, internationally. They have to keep up that standard, in order to make working for MESA+ desirable for the most talented researchers in the world.