Oxide growth on silicon: interface formation and nanoscale electrical properties
Promotion Date: 13 July 2006
| In our project we are looking for oxides with a larger dielectric constant than silicon oxide, the conventional gate oxide used for CMOS technology. With such a high-K oxide less leakage current occurs in very small transistors. We used atomic layer deposition, a method that saturates a surface with a single atom layer per deposition cycle. Chemical vapour deposition would have been an option, but with this technique it is difficult to control the growth for the large substrates that are used in the manufacturing process of the semiconductor industry. |
What was your thesis about?
In our project we are looking for oxides with a larger dielectric constant than silicon oxide, the conventional gate oxide used for CMOS technology. With such a high-K oxide less leakage current occurs in very small transistors. We used atomic layer deposition, a method that saturates a surface with a single atom layer per deposition cycle. Chemical vapour deposition would have been an option, but with this technique it is difficult to control the growth for the large substrates that are used in the manufacturing process of the semiconductor industry.
Is atomic layer deposition a new technology?
No, it is not new. I think it even goes back to the seventies of the last century.
But since we are looking for growth techniques for high-K gate oxides that can be easily upgraded from a laboratory technique to an industrial process in the semiconductor industry, the interest for Atomic Layer Deposition has considerably increased.
So what is your specific contribution?
We looked into the specific properties of the layers and suitable characterisation methods. We used scanning probe microscopy, not only checking the surface measuring the variations in height, but also measuring its electrical properties at the same time. We use a metal-coated tip for that.
Is your result the high-K oxide layer that industry has been waiting for?
It proves to be more difficult than expected to make an oxide layer that can be integrated in the current devices. The interface between the silicon and the oxide presents a problem: finding a surface treatment that gives a good interface quality proves to be difficult. We demonstrated that with our measurements.
But my most important result is the contribution towards the analysis technology of the electrical properties based on AFM and the fundamental research into the oxidation process of silicon.
What did you like best about your research?
Ahmmm, finding the method to also measure the electrical properties on the silicon oxide layer using AFM. In spite of the fact that oxide on silicon is extensively researched, we were able to make a definite contribution.
Any setbacks?
I had to wait more than two years for the AFM to be delivered and to be installed. I did not like that at all. Fortunately my contract was extended because of this problem.
What are you going to do next?
I would like a research job. A postdoc in the field of the physics of surfaces and interfaces or something.
For the summary of the thesis, click here.