PhD Defence Harijot Singh Bindra

Low Energy Design techniques for Data Converters

Harijot Singh Bindra is a PhD student in research group Integrated Circuit Design (ICD). His supervisor is B. Nauta from the Faculty of Electrical Engineering, Mathematics and Computer Science.

Internet of Things (IoTs) is an essential part of daily life and finds presence in a wide range of applications such as monitoring physiological signals, observing geophysical signals, monitoring plant health and agronomics, remote weather observation, embedded automation etc. In many use-case scenarios such as remote health care monitoring for heart patients, these IoT nodes are inaccessible and replacing batteries is not desirable. This makes it necessary for the sensor nodes to have long autonomous operating life without the need of much maintenance. Minimizing the average and peak energy consumption of each of the constituent blocks of an IoT sensor node not only allows for long autonomous operation but also reduces the size of the battery or the harvester energizing the IoT node, thereby making their integration easier in large-scale monitoring applications. Since the sensed physical signals need to be converted to the digital domain to be further used for signal processing, data transmission and manipulation, Analog-to-Digital converters (ADCs) form an indispensable block in IoT devices.

Successive Approximation Register (SAR) ADCs are the preferred choice for these Ultra Low Power (ULP) IoT applications owing to their high energy efficiency and an almost digital and asynchronous architecture which allows for scalability to optimize energy consumption over a wide range of these applications (few kS/s for biomedical to few MS/s for radios). However, the input (drive) circuitry responsible to present the (sensed) physical signals to a SAR ADC for signal acquisition and conversion has to be always ON in order to be able to detect any (critical) event without latency or loss of information. This calls for an energy centric design approach which is not only focused on minimizing the supply energy consumption of an ADC, but also minimizes the amount of energy required for driving its analog inputs to enable an overall low energy data acquisition system.

This thesis investigates design techniques to lower the energy consumption of both the ADC and its analog input drive circuitry.

The comparator is the only analog block in the otherwise digital SAR ADC architecture whose energy consumption does not scale in the same order with supply voltage as for the other digital blocks like control logic and DAC switching. Its energy consumption is dictated by the stringent quantization noise requirement at low supply voltage and, for medium resolution (8-12 bits) SAR ADCs the comparator constitutes 50%-60% of the ADC's energy consumption. This thesis introduces a dynamic bias comparator wherein the first stage : pre-amplifier is dynamically biased by virtue of a switched capacitor tail (CTAIL). This dynamic bias pre-amplifier has a self-quenching property wherein the complete discharge of the (noise) integrating capacitors (CP) at the pre-amplifier output drain nodes is prevented. This reduces the energy consumption of the pre-amplifier stage from the traditional  CP∙VDD2 value to CP∙VDD∙∆VDi, where ∆VDi is the voltage discharge on the drain nodes for a chosen CTAIL to CP ratio. The dynamic bias keeps the pre-amplifier operate in the weak inversion region of operation throughout the comparison period thereby maximizing its gm/Id to reduce the input referred noise. The performance of the proposed dynamic bias comparator in terms of its energy consumption, input referred noise and speed is shown. The implemented dynamic bias comparator is about 2.5 times more energy efficient than the latch-type comparator variant (Elzakker's comparator) where the output of the pre-amplifier discharges completely to ground. With an input referred noise of 0.4mV, the dynamic bias comparator makes an ideal building block for low-noise low-energy IoT applications.

The thesis then presents a range pre-selection sampling technique which aims at reducing the input drive current required for driving a SAR ADC sample capacitor. This technique is based on the fact that (three) different sample capacitors (DACs) are used to sample (three) different ranges of the input signal. The input signal before sampling is first compared to on-chip generated reference voltages (1/3rd and 2/3rd  of the supply voltage). Depending on the result of this comparison, the input signal is respectively sampled on one of the three DACs. This range pre-selection sampling technique minimizes the maximum voltage change (∆VDAC) at the sample (DAC) capacitors  to ideally one-third of the full-scale signal without compromising on the ADC's Signal-to-Noise Ratio (SNR). This reduction in ∆VDAC reduces the maximum input drive current and the energy required (CDACVDD∆VDAC) to drive the sample capacitors by a factor 3, thereby relaxing the input buffer requirements.

Most of the ULP SAR ADCs demonstrate their high energy efficiency at only a (few) fixed operating point(s). In addition these ADCs operate at low supply voltage (<0.5V) and use a large sample capacitor (approx. 1pF). This results in increased drive energy requirements where even the theoretical minimum energy (CV2) required to drive this sample capacitor is the same or larger than the energy consumption of the ADC itself. On the other hand the ADCs that demonstrate operation over wide range of sample rates have poor energy efficiency. Therefore for an ubiquitous operation, a 10b flexible SAR ADC architecture demonstrating high energy efficiency over a wide range of sampling rates and supply voltage without any loss in resolution is then presented. The asynchronous SAR ADC architecture incorporates the energy efficient self-quenched dynamic bias comparator and isolates its non-linear (parasitic) capacitor from the sample capacitor (DAC) thereby preventing distortion and degradation in linearity and resolution over the entire range of operation. The flexible SAR ADC architecture achieves a state-of-the-art Walden FoM of 0.35 - 2.5 fJ/conv-step over a wide sampling range (0.2 - 8MS/s) at corresponding supply voltage ranging from 0.7 - 1.3V with throughout >9b resolution and >66dB Spurious Free Dynamic Range. In order to relax the input drive energy requirement, an input range dependent swapping technique is used in this ADC. The differential inputs are compared with each other before sampling and depending on the comparison result (only) the upper and lower half of the input signal is respectively sampled on either half of the differential DAC. This (ideally) reduces the maximum change in voltage at the sample (DAC) capacitors and therefore the input drive energy requirement by a factor 2.

The thesis then demonstrates a buffered 10b differential SAR ADC wherein both the ADC and the Class-A buffers driving the ADC (differential) inputs operate at a single supply voltage and can handle near rail-to-rail input signal swing. Traditionally to handle rail-to-rail swing, a complimentary (NMOS and PMOS) input differential pair is required which results in signal dependent offset modulation and thereby distortion. Although increasing the size of the differential pair can reduce this distortion, this results in a large input capacitance and it still presents the challenge of minimizing input drive energy. The buffered SAR ADC architecture presented in this thesis makes use of the input signal range dependent swapping technique at the buffer inputs. As a result of this swapping of the input signal paths, the two buffers need to handle respectively (only) the upper and lower half of the input signal. This allows for the use of only a PMOS and an NMOS input stage in the respective buffers handling the lower and upper half of the input signal, thereby enabling the Class-A operation at the same supply voltage as the ADC itself. The proof-of-concept buffered SAR ADC can process near rail-to-rail inputs, consumes 149µW at 4 MS/s from a single 1.2V supply to result in a state-of-the-art Walden FoM (including buffers) of 87 fJ/conv-step and offers a high input impedance (due to swapping of the signal paths) that can be easily driven by a low power sensor, making it an excellent choice for IoT applications.

In summary this thesis presents design techniques to reduce the amount of energy required to perform various operations during data conversion, such as comparison, buffering the input signal and sampling the  buffered input signal. These techniques aim at reducing the amount of charge (and energy) required to perform each of these operations that require a certain capacitance to satisfy the theoretical kT/C noise limit for a given SNR. The energy consumption for charging-discharging of this capacitor is reduced by minimizing the voltage change across this capacitor for the operations mentioned above without compromising the SNR. The low energy design techniques presented in this thesis contributed towards attaining the lowest reported Walden FoM of 0.35 fJ/conv-step for the standalone SAR ADC. When including the energy consumption of the buffers the Walden FoM of 87 fJ/conv-step (using only a single supply voltage) is also the lowest among all the reported buffered SAR ADCs to the best of my knowledge.