UTFacultiesEEMCSEventsPhD Defence Anoop Bhat | Wide Band Linearization Techniques for RF Receiver Front-Ends

PhD Defence Anoop Bhat | Wide Band Linearization Techniques for RF Receiver Front-Ends

Wide Band Linearization Techniques for RF Receiver Front-Ends

The PhD defence of Anoop Bhat will take place (partly) online and can be followed by a live stream.
Live stream

Anoop Bhat is a PhD student in the research group Integrated Circuit Design (ICD). Supervisor is prof.dr.ir. B. Nauta and co-supervisor is dr.ir. R.A.R. van der Zee from the Faculty of Electrical Engineering Mathematics and Computer Science (EEMCS).

This thesis presents wideband linearization techniques for RF receiver front-ends. The thesis is divided into two parts. The first part proposes a wideband-IF, linear, down-conversion-based receiver front-end mainly for cognitive radio applications. The second part presents a wideband, linear active balun capable of driving gigahertz ADCs up to their full-scale input voltage for direct RF-sampling applications.

Driven by Moore's law, transistors have become faster and more compact, increasing the digital capability of a system significantly. The performance of the RF front-ends succeeding or preceding the digital blocks also needs to be increased to match the advances in the digital domain. Data acquisition and communication are examples of such systems where a significant increase in the performance of the RF front ends is paramount. RF receiver front-ends are one of the main constituents of these systems and this thesis focuses on increasing their linearity and bandwidth. RF receivers can be realized primarily either as down-conversion-based or as direct RF-sampling-based. This thesis contributes to increase the linearity and bandwidth in the applications involving both types of receivers.

A traditional down-conversion-based receiver architecture has evolved over the decades. Several outcomes of this evolution have benefited a receiver's linearity and bandwidth. An example is a mixer-first receiver, the evolution of which has increased a receiver's achievable linearity to an extent that many recent works target to remove the pre-select filter in the receiver's signal chain. Nevertheless, while targeting high in-band linearity, existing mixer-first receiver architectures show various trade-offs with other performances. This thesis analyses a trade-off that exists between the in-band linearity and NF of the mixer-first receivers in detail, including deriving corresponding symbolic expressions and graphical illustrations. The trade-off that exists between the linearity and RF frequency range of an LNTA operating at RF frequencies is also analysed with detailed simulations. A baseband-matching-resistor noise-cancelling receiver architecture is proposed in this thesis which breaks these trade-offs. Furthermore, to achieve high linearity over a wide TIA bandwidth, a three-stage inverter-only OpAmp with 7.6GHz UGB is designed. The inverter-only design favours its redesign and reuse with the scaling of the technology. The proposed receiver realized on-chip in an FDX 22nm CMOS process measures >9dBm IIP3 over 175MHz TIA bandwidth. The measured NF varies between 2.5 to 5dB in the frequency range between 1 and 6GHz.

With the recent advances, gigahertz ADCs support >8bit resolution over >4GHz. Besides the gigahertz ADC, realizing a high-performance balun preceding it is challenging. This balun needs to deliver high voltage swings to the input of the ADC with high linearity over a wide bandwidth. Existing baluns do not favour CMOS integration as they are either off-chip and passive or are fabricated using exotic non-CMOS processes. Existing CMOS active baluns mainly focus on down-conversion-based receivers and are not capable of delivering high voltage swings.  A wideband CMOS active balun achieving high linearity up to high voltage swings is proposed in the second part of this thesis. The circuit consists of an LNA at the input followed by an actual balun and the driver blocks. Since the driver blocks experience higher i/o voltage swings compared to other blocks, a PVT robust pre-distorter circuit is used to reduce their distortion. All the circuits are derived from a common highly linear building block (HLBB). The HLBB is evolved from an inverter with strong source degeneration whose dominant nonlinearity mechanisms are analysed in detail. The derived symbolic expressions and simulation results show that there is a limit to increase the strength of source degeneration, after which the linearity benefits are not obtained. A bootstrapping technique is employed in the HLBB to extend this limit and continue to obtain the linearity benefits of the source degeneration. The CMOS active balun fabricated on-chip in an FDX 22nm CMOS process measures < −44dBc HD3 up to 1.5Vp-p over 0.01-5.4GHz. The measured CP1dB corresponds to 2.8Vp-p. The measurement results confirm that all the linearization techniques proposed are robust to PVT variations.