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PhD Defence Xingyu Liu | Low temperature pure boron layer deposition for silicon diode and micromachining applications

Low temperature pure boron layer deposition for silicon diode and micromachining applications

Due to the COVID-19 crisis the PhD defence of Xingyu Liu will take place (partly) online.

The PhD defence can be followed by a live stream.

Xingyu Liu is a PhD student in the research group Integrated Devices and Systems (IDS). His supervisors are prof.dr. J. Schmitz and prof.dr. L.K. Nanver from the Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS).

In this thesis, the research on silicon-based PureB technology was extended from the original work performed by depositing pure boron in a state-of-the-art commercial Si/SiGe ASM Epsilon epitaxy system, to other deposition methods and less optimal deposition conditions. This included lower substrate temperatures, much faster deposition rates, and higher susceptibility to oxygen contamination. To study the effects on the B-layer and PureB diode properties, several electrical characterization and chemical analysis techniques were developed to evaluate the usability of the as-deposited B-layers. In addition, the B-layer was established to be attractive both as a masking layer for Si anisotropic etching and as a membrane material.

The properties of PureB diodes are discussed in relationship to the behavior of conventional diffused p-n diodes and their application as photodiodes. PureB diodes with a nanometer-thin pure B layer as the anode region on n-type Si, were in the past shown to have deep-junction-like I-V characteristics. The physical model proposed to explain this behavior was that a high density of acceptor states is formed at B-Si interface. These fill with negative charge that attracts an inversion layer of holes and this interfacial hole layer functions in the same manner as would be expected for a B-doped p+-region. While this interface bonding is largely responsible for the electrical characteristics, the capping layer of bulk B provides a robust protection of the interface.

In the past, the 400℃ and 700℃ chemical-vapor deposition (CVD) of B in the Epsilon was given most attention, the latter being electrically and chemically very robust and former having the advantage of being back-end CMOS compatible. Both displayed I-V characteristics that were similar to conventional deep diffused p+n junction diodes. In this thesis, B-deposition in three other ways was investigated. CVD was performed in the Picosun ALD system using 5% B2H6 in Ar, where in-situ growth monitoring was possible. Batch furnace low-pressure and ultra-low-pressure CVD systems (LPCVD and ULPCVD) systems were compared. These systems allowed deposition temperatures down to about 200°C. For room-temperature deposition a molecular-beam-epitaxy (MBE) system was used with the advantage that the layer thickness was independent of the substrate temperature. The B-layer thickness and uniformity, as the key parameter in this research, was monitored by ellipsometry.

In Chapter 3, several electrical test structures were developed to study the current flow in PureB diodes with respect to different fabrication procedures. Vertical pnp transistors with emitter regions made with PureB diodes are ideal for measuring the electron injection into the B-region but demand several diffused regions. Lateral pnp’s with emitter and collector region made with PureB diodes much more are straightforward to process but parasitic base current prevents the extraction of the electron injection into the B-regions. A 2-diode measurement technique making use of the lateral pnp structures, was studied. It made use of the interaction of hole currents spreading into the substrate to help distinguish whether the diodes were pn-like or Schottky-like. These transistor test structures had Al-metallization of the contacts, which for thin B-layers sometimes degraded the interface that was important for the PureB diode characteristics. Therefore, to enable an electrical evaluation of the as-deposited B-layers, non-metallized test structures were developed, making use of implanted p+ regions to contact the B-layer. Test structures for measuring the sheet resistance, Rsh, along the B-Si interface were used to evaluate the degree to which the electrically active B-Si bonds were created. A method was also found for extracting the electron injection, Ie, into PureB regions fabricated at low temperatures where it became comparable to the hole injection, Ih, into the n-substrate.   

Chapter 4 introduced the B-layer as masking layer for wet anisotropic Si etching in TMAH or KOH. The etch rate in these etchants was also used to evaluate the compactness and integrity of the B-layer. For Epsilon B-layers deposited at 400℃ or 700℃, layers as thin as 2nm were resistant to the Si etchants, but some pre-depositions treatments were found to weaken the integrity of the layers in this respect. For example, 400℃ B-deposition on implanted p+-regions the Si under the B-layer was attacked by the etchants.  The appearance of separated cavities after exposure to an etchant suggested that isolated weak spots were present in the B-layers. Among several 1 nm 400℃ B-layers, cavities on non-implanted region were found in one sample after 6 min TMAH etch at 65 ℃. The density of these small pyramid-shape cavities was too low to lead to a connected fully-etch surface area, meaning at 400℃ the coverage was almost complete after deposition of first few atom layers. The B-layers were found to be effectively etched by standard Al etchant, so patterning with photoresist was possible. After long-time Si etching on patterned B samples, a very low lateral undercut was observed, demonstrating a good adhesion of B and Si. B-membranes were left across the corners cavities etched through circular openings in B-masks. The topography of these B-membranes, as observed by optical microscopy, revealed that the stress in the membranes varied a lot depending on deposition conditions.

In Chapter 5, a number of B-depositions from 450℃ down to room temperature were studied using the electrical characterization techniques and etch tests developed in Chapter 3 and 4. The Si surface cleaning before deposition was shown to be crucial for establishing the desired B-Si bonding at the interface. The most reliable cleaning method was found to be the traditional native oxide removal by HF dip-etching. Several extra cleaning treatments were investigated with the purpose of guaranteeing the free oxide surface, such as exposure to high-temperature H2 annealing or vapor HCl. However, these extra steps appeared to have a negative impact on the perfection of Si surface. Moreover, in the Epsilon it was found that keeping the substrate in the load-lock for N2 purging could reduce the oxygen/moist brought into the system and significantly lower the oxygen incorporation in the layer during the deposition. Post-deposition annealing at higher temperatures also improved the electrical properties by doping the Si with B.

B-layer depositions under 450℃ were performed in the Picosun, the ULPCVD furnace and the MBE system.  In the Picosun, depositions from 450℃ to 200℃ were performed, and the growth of the layers showed a supposedly self-limiting behavior with the 250℃ B-layer thickness measured to be 1 nm to 1.5 nm by in-situ ellipsometry. The presence of a B-coverage at 200℃ and 250℃ was confirmed by SIMS, and B-concentration was higher at 250℃. The 250℃ B-layer gave Ie and Rsh values close to those of 400℃ PureB diodes while the 200℃ layers gave a very high Rsh. Adding a 400℃ deposition brought the sheet resistance of the 200℃ sample down to the same order with 400℃ while the 250℃ sample was not significantly changed, showing that the potential B-Si bonding at these low temperatures is about the same. MBE PureB diodes with ~ 2-nm-thick B-layers were made with deposition temperatures from 50℃ to 400℃. The electrical results were similar to the CVD layers except for the very low temperature MBE B-depositions at 200℃ and 50℃ that had a much higher gave Ie and Rsh values.

The furnace ULPCVD system enabled batch processing, but with the disadvantage that the selectivity and thickness control of thin layers was poor. A 10 nm deposition on Si was already enough to grow an electrically connected layer on oxide. The back-etching of the B-layers in Al etchant was investigated as a means of chemically thinning the layers. Even after extensive etching, the Al etchant could not completely remove B atoms on Si. SIMS analysis showed that for low temperature deposition without bulk doping, the number of B atoms left after extensive etching was about a decade less than expected for a complete monolayer. Hence, oxidation of the etched samples was imminent and high Ie and Rsh were found.

As discussed in Chapter 6, B-layer research in other groups had led to the realization that these layers had a transmissivity and emissivity that made them potentially suitable for use in EUV pellicles. If stand-alone B-membranes were to be applied, the requirements on the robustness and flatness of the membrane would be high. Several B-deposition conditions were studied with this in mind. At 400℃ the Picosun layers were slightly tensile and several millimeter large membranes, tens-of-nanometer to a micrometer in thickness were successfully fabricated. The B-layers grown in the Epsilon from 400℃ to 700℃ were characterized by compressive stress that approached zero at about 600 ℃. The Picosun B-layers grown from 300℃ to 500℃ had tensile stress that decreased with temperature to values so low that at 300℃ they were not measurable. This tensile stress increased as the deposition temperature and/or rate increased. With respect to the masking of TMAH Si etching, all layers were suitable. However, while the Epsilon B-layers gave sufficient protection when only a few nm thick, the low-temperature Picosun B-layers needed to be thicker due their low compactness and more susceptibility to Si surface contamination. With a Picosun deposition at 400℃, a 60-nm-thick B-membrane, 7 × 7 mm2 in size, was made by through-wafer etching. These thick layers were, however, more prone to break spontaneously or to be very fragile. This was particularly true B-layers grown in the ULPCVD furnace, and if the deposition rate was high. There were also indications that it could be beneficial for the strength of the membrane to intentionally introduce a bit of oxygen contamination. In this way a 1-µm-thick B-membrane with an area of 3 × 3 mm2 was successfully demonstrated.