Due to short time to market and reuse of designs, System on Chip (SoC) architectures that are composed of commercially of-the-shelf available intellectual property (IP) blocks are becoming popular. There is a trend to develop (reconfigurable) SoC architectures that are flexible enough to run a range of applications within a certain domain. Common practice is to map applications to SoC architectures at design-time. An application is modeled as a set of communicating processes. For a number of reasons (e.g. dynamic resource management, adaptation to required resources and yield improvement) it is preferred to perform the mapping at run-time.
The main research question is to provide the theoretical framework for efficient and flexible mapping/optimization algorithms that can be used at run-time. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required Quality of Service.