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Real-Time Scheduling and Control in Testing of Chips

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Funding: Agentschap NL, Provincie Overijssel
Running Period: 2009-2013
Staff: Johann Hurink, Gerard Smit
Ph.D. student: Harm Bossers  


For all manufacturers, it is important that their products meet certain quality and reliability criteria. In general, there are several ways to ensure a certain degree of quality, but testing of each individual product is usually not necessary. This is different in the semiconductor industry with a production process being very sensitive to a wide range of factors which could influence the quality. Furthermore, chips are used in a wide range of critical applications. Therefore, testing of each individual chip is required, before it can be shipped to a customer. The testing process consists of two main steps: wafer test and final test. During wafer test, all devices are tested while still on the wafer. Then the wafer is sawed and all devices are assembled into packages. Then these packaged devices are tested again during final test.

Although there are limits (in time and costs) to which extent a chip can be tested, customers are always demanding higher delivered quality against lower prices. Therefore, semiconductor manufacturers are eager to find methods which can be used to control reliability and save costs of the testing process. Besides technical developments, another concept is emerging: Adaptive Testing. Adaptive Testing is a very broad term, referring to the use of statistics and data analysis in order to change test limits, flows and content. This can include feed-forward data from early tests in the production process to later test steps and feed-back data to optimize testing of future products.

The use of statistics in chip testing has emerged past decade, resulting in a wide range of papers. However, most papers describe post-processing methods and hence are only applicable to wafer test, where data analysis can take place after testing of a complete wafer. This is because devices still can be tracked and identified based on their coordinates. In final test, immediate decisions are required, then the device is gone and cannot (or only at high costs) be identified. Mostly these methods try to estimate test responses if the chip would be healthy and compare these estimates with the real measurements. Then outlier detection methods are applied to the resulting residuals to identify (possible) faulty chips. Estimations are made by for example exploiting wafer spatial patterns and correlations between tests.

The goal of this project is to develop statistical methods which can be used to achieve both test costs savings and/or a higher reliability of the tested chips. These methods should be applicable to the final test phase, and thus the described restrictions in final testing should be taken into account. Furthermore, research will be performed on real-time scheduling and data streaming. Efficient application and automation of developed statistical methods also requires (real-time) scheduling and data streaming methods such that those automated tasks can be executed in an efficient matter with minimal impact on total testing time.