Dependable Computing Systems

With a focus on low-level security features, we explore hardware vulnerabilities that can affect devices in the field, be they on the ground or in space. While encryption standards might be theoretically secure, their implementations might leak information or provide easy-to-exploit vulnerabilities. Our group explores these vulnerabilities found on commercial devices and proposes countermeasures that can be implemented both in software and hardware (full stack). Our investigations cover:

• Side-Channel Analysis and attacks
• Fault Injection campaigns
• Development and investigation of Roots-of-Trust
• Hardware security primitives
• Secure IPs and accelerators

Space, automotive, and medical devices are safety-critical systems, where it is necessary to provide guarantees to the availability and reliability of the system and service. As technology has improved, we've been able to fit more and more hardware onto each computer chip. Smaller technology nodes make them more vulnerable to defects and Single Event Upsets (SEUs) from ionizing particles. We investigate reliability techniques, that can provide these assurances, our efforts include:

• Characterization of devices under ionizing radiation exposure
• Implementation of hardware and software reliability schemes
• Development of reliable IPs and accelerators

The DCS group works with many partners, from the private and public sectors, in industry and academia. This research leads us to projects and topics that align with state-of-the-art research for space reliability and the security domain. Some of our partners include:

• European Space Agency (ESA)
• Technolution 
• Riscure 
• ETHZ
• University of Rome Tor Vergata

These are the current thesis from our students. To find the currently available thesis, look at the bottom of this page.

• HW accelerated SCA trace alignment, Joep Bakker
• Improving the design flow of fault resilient hardware via Fusa tooling, Simon Balk
• Hardware-orieneted security assessment of PQC systems, Marijke van Iperen
• Side Channel leakage assesment of PR systems, Niek Vincent
• Countermeasures for SCA through variants in PR systems, Quinten Nijkrake
• Reliability Analysis and Optimization of Tree-Based Machine Learning Models, Jelle Berning
• Evaluation of Timing countermeasures for SCA, Bas De Quinze

These are the current thesis from our students. To find the currently available thesis, look at the bottom of this page.

• Evaluation of DelayAVF Emulation in a softcore, Pieter Paasman

Our Alumni have finished their projects and are now making the world a safer and more secure place. Find their work here:

2026

• Taming Algorithm Execution for Racetrack Memory, Vladimir Halchenko, MSc
• Complexity-Performance Trade-Offs in Hybrid Beamforming and OTFS for LEO Satellite Systems: an FPGA Implementation Perspective, Mateusz Budnik, MSc
• Trade-Off Analysis of Error Correction Codes, Interleaving, and Scrubbing for Mitigating Multiple-Cell Upsets in Memory Systems, Jurren Doppenberg
• Stress Behaviour in Weakly Hard Real-Time Systems, Stijn Brugman

2025

• Performance Analysis of the NEORV32 CPU Implementation on a SmartFusion2 FPGA with BRAM and Flash Memory, Tycho Schurink, BSc
• Middleware for Distributed System, Armin Purle-Kopacz, MSc
• Designing an Emulation Framework for Modelling Delay Fault Vulnerability : Accelerating Delay Fault Analysis through FPGA-based Dynamic Delay Injection, David Postema, MSc
• Optimising a Bloom Filter based instruction checker for embedded applications, Frank G. W. Kok, MSc
• Designing a RERI-based error logging system for RISC-V cores, Michiel Koenderink, MSc
• Vendor-Unlocked Scalable Adaptive Random Forest Accelerator, Ewout van Nimwegen, MSc
• Compiling a RISCV extension for Skyrmion Racetrack Logic-in-Memory using the Clang Compiler, Larissa van Deinse, MSc
• Accelerating AVF analysis using statistical fault injection, Kevin Schrama, MSc
• Exploring power trace capture setups for side-channel analysis using the test-vector leakage assessment on a RISC-V target, Jasper T. Vinkenvleugel, MSc
• Improving Radiation Tolerance for Neuromorphic Processors, Wim Nijsink, MSc
• Customized Processing-in Memory designs, Marten H. W. Trip

2024

• Fault Injection Attacks on Trusted Execution for RISC-V Cores, Remco van Dijk, MSc
• Implementation and Evaluation of an Embedded AI System on a Resource-Constrained Platform, Nezar Sanad, BSc
• TrackScorer: Skyrmion Logic-In-Memory Accelerator for Document Ranking, Martijn Noorlander, MSc
• Investigating RISC-V hardware for autonomy in space, exact emulation-based fault injection on a hardware accelerator, Tijmen Smit, MSc
• Evaluating the effectiveness of Test Vector Leakage Assessment when performed on Kyber running on a softcore RISC-V processor on an FPGA, Mathijn Becker, BSc

2023

• Design and evaluation of a Ring Oscillator based Physically Unclonable Function, Mateusz Budnik, BSc
• Observability of off-the-shelf microarchitectures based on the RISC-V Instruction Set Architecture, Wouter van Huffelen, MSc
• Fuzzing: A Comparison of Fuzzing Tools, Suhas Belle Lakshminarayan, MSc
• Towards Future Proof Cryptographic Implementations: Side-Channel Analysis On Post-Quantum Key Encapsulation Mechanism CRYSTALS - Kyber, Jelle Meijer, MSc
• Radiation resilience evaluation of a Flash-based FPGA with a soft RISC-V core, Kevin Böhmer, MSc
• Evaluation of On-line Reconfiguration Techniques for a Distributed Avionic Middleware., Glen te Hofsté, MSc
• A Simple Homomorphic Obfuscation Scheme over Automorphisms, Lars Willemsen, MSc

2022

• Preventing Soft Errors and Hardware Trojans in Embedded RISC-V Cores, Edian Annink, MSc
• Reliability Analysis of Triple Modular Redundancy, Stijn Nowee, BSc