Welcome to the Computer Architecture for Embedded Systems (CAES) group of the Faculty of Electrical Engineering, Mathematics and Computer Science of the University of Twente in the Netherlands.
Anuradha Ranasinghe and Sabih Gerez have received the best paper certificate in the track Logic and Circuit design of the ICCD 2020 (https://www.iccd-conf.com/Home.html) Oct. 18-21, 2020. Title of the paper "MEPNTC: A standard Cell Library Scheme, Extending the Minimum Energy Point Operation of Near-Threshold Computing".
On the 2nd of October, Victor Reijnders won the third prize for Best Student Paper Award at ENERGYCON 2020 [https://ieee-energycon2020.org/awards/]. The conference covers a broad range of electric power and energy systems topics, and had over 190 accepted papers. ENERGYCON 2020 would have taken place in Tunisia, but was now held online due to Corona. Victor presented a hybrid electricity pricing mechanism, combining both system optimization and socal acceptability goals, research which was done together with Marco Gerards and Johann Hurink. [https://research.utwente.nl/en/publications/a-hybrid-pricing-mechanism-for-joint-system-optimization-and-soci]
We congratulate Victor with this award!
Hans Kerkhoff and Ahmed Ibrahim have received the best paper award at the International Test Conference - Asia 2019 in Tokio, Japan. The title of the paper: An On-chip IEEE 1687 Network Controller for Reliability and Functional Safety Management of System-on-Chips
Baver Ozceylan (DACS), assistant professor Marco Gerards (CAES) , Maurits de Graaf (Thales Netherlands) and prof. Boudewijn Haverkort (Tilburg University) received the Harvey Rosten Award for Excellence for their paper "A Generic Processor Temperature Estimation Method". In this research, the authors describe how to model the temperature of a processor based on limited measurements and several (performance) parameters. This research was done within the "Dependable Autonomous Mobile Computing" project, which is part of the ZERO Energy program.
The spin-off company QBayLogic started its services in FPGA design, based on the compiler CλaSH that translates mathematical specifications of FPGA architectures into a traditional hardware description language. The compiler CλaSh is developed by of the CAES-group, over a period of eight years, resulting in many publications and several PhD theses. We are proud that this period of fruitful rearch resulted in a spin-off company to transfer the developed techniques to the market.