Welcome to the Computer Architecture for Embedded Systems (CAES) group of the Faculty of Electrical Engineering, Mathematics, and Computer Science. The CAES group conducts research and education in computer architecture and computing systems with a particular emphasis on embedded systems.
Embedded systems are already commonplace, they provide the necessary control and integration of cyber-physical systems. In the last couple of decades, a larger portion of the world’s total computing power is taking place at the edge, motivated by broad concepts, such as the Internet-of-Things (IoT), machine learning, smart grids, and real-time and dependable systems. With different constraints in terms of power consumption, performance, reliability, and security, the understanding of the underlying computer architectures is vital for the efficient integration of these systems.
Our research goal is to investigate the challenges and opportunities in the intersection between CS and EE. This large scope allows our researchers to tackle real problems with a broad and systemic view, allowing for the development of new technologies, architectures, design automation tools, algorithms, methodologies, and models. This process requires knowledge from different domains in the hardware and software levels of abstraction, allowing ample space for our members to develop and collaborate internally and with external partners.
Outstanding Reviewer Award from International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) 2024 Best Paper Award ECRTS 2023, "On the Equivalence of Maximum Reaction Time and Maximum Data Age for Cause-Effect Chains" Euromicro Conference on Real-Time Systems, Vienna, July 2023. Mario Günzel, Harun Teper, Kuan-Hsun Chen, Georg van der Brüggen, Jian-Jia Chen, "On the Equivalence of Maximum Reaction Time and Maximum Data Age for Cause-Effect Chains"
Best Paper Award IEEE DFT 2022, "Preventing Soft-Errors and Hardware Trojans in RISC-V Cores" IEEE DFT 2022, 35th International Symposium on Defect and Fault Tolerance in VLSI and Nantechnology Systems. October 19th-21st, Austin, Texas (USA).
Edian Annink, Gerard Rauwerda, Edwin Hakkennes, Alessandra Menicucci, Stefano Di Mascio, Gianluca Furano, and Marco Ottavi, "Preventing Soft-Errors and Hardware Trojans in RISC-V Cores"
QBayLogic: a spin-off company of the CAES group The spin-off company QBayLogic started its services in FPGA design, based on the compiler CλaSH that translates mathematical specifications of FPGA architectures into a traditional hardware description language. The compiler CλaSh is developed by of the CAES-group, over a period of eight years, resulting in many publications and several PhD theses. We are proud that this period of fruitful rearch resulted in a spin-off company to transfer the developed techniques to the market.