Welcome to the Computer Architecture for Embedded Systems (CAES) group of the Faculty of Electrical Engineering, Mathematics and Computer Science of the University of Twente in the Netherlands.
In autumn 2016 the spin-off company QBayLogic started its services in FPGA design, based on the compiler CλaSH that translates mathematical specifications of FPGA architectures into a traditional hardware description language. The compiler CλaSh is developed by of the CAES-group, over a period of eight years, resulting in many publications and several PhD theses. We are proud that this period of fruitful rearch resulted in a spin-off company to transfer the developed techniques to the market.
On Friday the 5th of February, PhD candidate Robert de Groote successfully defended his PhD thesis, entitled "On the Analysis of Synchronous Dataflow Graphs - a system-theoretic perspective". Robert was awarded a PhD degree with honours ('cum laude'). Robert continues his work in the CAES group as a postdoctoral researcher, on the project POLCA, where he applies synchronous dataflow to the modelling of regular computational structures, and their mapping onto heterogeneous hardware architectures.
Jordy Huiting, a PhD student of the CAES group, was awarded the Best Paper Award at the 5th international EURASIP workshop on RFID technology, RFID'2015, held October 22-23 in Rosenheim, Germany. Jordy's paper is enttitled:
"Near field phased array DOA and range estimation of UHF RFID tags".
H.G. Kerkhoff and H. Ebrahimi have won the best paper award for their paper titled "Intermittent Resisitive Faults in Digital CMOS Circuits". The paper is published in IEEE 18th International symposium on design and diagnostics of electronic circuits and systems, held 22-24 April 2015 in Belgrade, Serbia.