Koray Karakaya

Ph.D. thesis

Thesis title:

CeO2 and HfO2 high-K dielectrics by pulsed laser deposition: from binary oxides to nanolaminates

[thesis in pdf format]




Prof. Dr. Ing. D.H.A. Blank

Assistant promotor:

Dr. Ing. A.J.H.M. Rijnders

Date defense:



Since the early years of integrated circuit (IC) technology, the complexity of the IC devices has increased continuously as predicted by the famous Moore’s Law. Instead of being a law of physics, this is a self fulfilling prophecy, which is later formed the basis of the technology development roadmap. As of 2006 most of the central processing units (cpu) are produced at 90 nm level (the size of a transistor in an IC) and even 65 nm devices are recently introduced. For emphasizing the effect of scaling trend it’s good to remember that just a decade ago device dimensions were in level of 500 nm. The gate dielectric thickness, which is typically 1/25 of the gate length, is also decreased accordingly to achieve a good channel control, which can be defined by the terms of gate capacitance. The thickness of the state of the art dielectrics (SiO2 and SiON) are below the tunneling limit and doesn’t meet the gate leakage requirements defined in the International Technology Roadmap for Semiconductors (ITRS). High-k gate dielectrics are introduced as a solution for overcoming the gate leakage problem by maintaining the same gate capacitance levels. According to the simple parallel plate capacitor relation, the same gate capacitance level can be achieved with a thicker dielectric layer which has a higher dielectric constant than SiO2 and SiON. Larger physical thickness of the gate dielectric helps overcoming the gate leakage problem. A number of materials have been proposed as high-k gate dielectrics on silicon. However, still a manufacturable solution for near term expectations is not found.

A suitable high-k dielectric material has to have high permittivity, a large barrier height (~4-5 eV), thermodynamical stability on silicon, high interface quality, gate electrode compatibility, reliability and of course the process compatibility. In the search for a new material with these properties Pulsed Laser Deposition (PLD) is one of the most powerful tools. It has a number of advantages like independent control of process parameters, layer control in the atomic level, ability of using multiple target materials for multilayer depositions and fast processing compared to the other deposition methods makes PLD an attractive tool for materials research. In this work, PLD is used for deposition of CeO2 and HfO2 layers. Different processing conditions were investigated from oxidizing to reducing ambient deposition, in-situ post deposition anneal, binary oxides as well as the laminated layers of CeO2 and HfO2.

The pre-deposition treatments, i.e. native oxide removal and thermal treatment, and deposition conditions are discussed in Chapter 2. It is found that the pre-deposition anneal of hydrogen passivated silicon substrates improves the layer quality and also affects the hydrogen presence in the layers as indicated by secondary ion mass spectrometry (SIMS). Next to the substrate treatment, special emphasis has been given on the use of a reducing ambient followed by an in-situ high oxygen pressure post deposition anneal (PDA). It is shown that the crystalline orientation of CeO2 layers depends on the ambient conditions: (111) orientation has been found using reducing conditions, whereas the layers grown in oxygen were randomly oriented.

In Chapter 3 the properties of the CeO2 and HfO2 binary oxides, are discussed. A thickness series of the layers from 4 to 16 nm were deposited at 420 and 520 oC followed by an in-situ PDA with a 5 oC/min cooling rate. Analyses showed that the crystallinity of the layers is thickness dependent. As the layer thickness increases, the layers evolve to a polycrystalline structure with a preferred orientation. This polycrystalline structure alters the electrical properties drastically, increases the leakage current in particular. The best leakage current reduction is achieved by CeO2 layers deposited at 420 oC with two orders of magnitude lower than SiO2 reference data. However, 4 nm HfO2 layers deposited at 520 oC is showed the lowest equivalent oxide thickness (EOT) of 0.95 nm. Fixed charge density (Qf) of the CeO2 layers in level of 5x1011 cm-2, is found to be two orders of magnitude lower than HfO2 layers. The anomaly of the k value of the CeO2 layers extracted by the EOT-physical thickness (EOT-tph) plots was attributed to the thickness dependent crystallinity of the layers. Increased crystallinity in thicker layers results in lower EOT values hence reduces the slope of the linear fit on the plot.

Investigating the properties of the laminated structures of CeO2 and HfO2, called as nanolaminates, was the major aim of this work. The basics of the lamination, i.e. the layer sequence and the individual layer thickness are presented in the first part of Chapter 4. Effect of the deposition ambient, deposition temperature, cooling rate during in-situ PDA, effect of the oxidation time during PDA were discussed. Modification of the Si– high-k interface by depositing a cerium metal interlayer prior to high-k deposition is also given in Chapter 4. It’s found that the Si‑HfO2 interface promotes the crystallinity of the layers compared to the Si‑CeO2 interface. Comparison of binary CeO2 layer with the laminated structure with a Si-CeO2 interface showed that the lamination diminishes the crystalline phase formation. The crystalline phase formed in the CeO2/HfO2 nanolaminates is likely to be CeHfO4 according to the fast Fourier transform (FFT) analyses on the transmission electron microscope (TEM) images of the layers. However, one should note that this structure is nearly identical to (111) CeO2 and HfO2. Individual layer thickness on the laminates is found to be affecting the capacitance-voltage (C-V) hysteresis of the layers: As the individual layer thickness increases, the C-V hysteresis increases up to 2 V. This behavior is correlated to the formation of a crystalline phase in the case of increased individual layer thickness in the laminated structure. Investigation of the effect of deposition temperature and different in-situ PDA conditions also showed that the layers’ properties are strongly depending on their crystallinity and the crystallinity is not only affected by deposition temperature and PDA parameters, but the layer thickness as well. The best leakage current reduction, almost six orders of magnitude lower than SiO2 reference data, is achieved by the 4 nm layers deposited at 420 oC and the PDA with a 2 oC/min cooling rate.

Improvement of interface properties by means of cerium metal interlayer showed that the interface oxide thickness didn’t improve significantly. However, orientation of the laminated structure is found to be improving by this application. An epitaxial structure on top of the amorphous interface oxide is observed by TEM in the 8 nm laminate with a cerium metal layer deposited at room temperature (RT). The 4 nm laminate grown at 520 oC, with a cerium interlayer deposited at RT gave an EOT of 1.9 nm and a leakage current reduction of six orders of magnitude lower than SiO2 reference data.

Fabrication of metal oxide semiconductor field effect transistors (MOSFET) with CeO2/HfO2 nanolaminates are presented in Chapter 5. Formation of an upper interface between the high-k layer and the aluminum gate electrode was observed. Intensive analyses on the interface showed that the composition is amorphous Al2O3. A significant aspect of the devices with Al2O3 upper interface was the interface between the silicon substrate and the high-k layer, which was in level of a monolayer thickness. This is showed that the Si – high-k interface can be reduced by the gate metal to form an upper interface. However, the presence this non-uniform upper interface layer and the subsurface defects in the channel region decreased the device performance. Subsequent interface oxide formation during device processing (i.e. plasma etching of TaN electrodes) is also given in the final part of Chapter 5.

The details of the techniques used for electrical characterization of the high-k layers investigated in this thesis are given in Appendix 1. In Appendix 2, the details of electrode processing for device fabrication are presented.