Chiptech

Advances in silicon (Si) nanomachining are crucial for the development of next-generation electronic and magnetic nanodevices. As conventional two-dimensional (2D) downscaling approaches fundamental and economic limits, achieving higher areal density requires well-defined three-dimensional (3D) nanostructures. These 3D architectures can serve as templates for integrating functional materials, thereby enabling novel device concepts. Crystallographic nanolithography has emerged as a promising route towards wafer-scale fabrication of functional 3D silicon nanostructures. This method exploits the crystallographic properties of silicon in combination with self-aligned methods such as corner lithography and retraction edge lithography to enable precise geometrical control in nanoscale. Recent work demonstrates progress in the fabrication of high-density 3D silicon nanostructures for electronic and magnetic applications. Self-aligned p-type silicon nano-wedges have been employed to realize gated platinum silicide (PtSi) geometric diodes showing interesting device performance. Furthermore, wafer-scale “nano-tables” have been developed as templates for magnetic racetrack memory, highlighting the potential of this method for scalable memory technology. Looking ahead, crystallographic nanolithography provides a pathway toward fully 3D architectures, opening new opportunities in the design and integration of electronic and magnetic nanodevices.

Relentless scaling in CMOS integrated circuit technology enabled the tremendous computing power we now carry in our pockets every day (Moore’s Law). This made quantum effects, such as tunneling, a serious problem. In our “Vision”, these “Tunnel” currents in MOS-transistors should not be considered an undesired energy-leaking effect as is common practice today, but a fundamental property that can be exploited in ultra-low-power circuit design, e.g. to boost battery lifetime of the billions of Internet-of-Things devices. In our recently granted TunnelVision project in the NWO-OTP programme, we intend to achieve this by cross-domain research in physical/compact modeling and characterization, and disruptive ultra-low-power analog integrated circuit design in modern industrial CMOS process technologies. In this short introductory talk, we'll explain why gate leakage is here to stay, what the limitations are of modern ultra-low-power CMOS design, and why gate-leakage-based circuitry as envisioned in TunnelVision may solve these limitations.

Microfluidic devices can automate and simplify biological and chemical workflows. However, designing them is still labour-intensive. Fluidic networks require a well-designed physical layout, as both components and connecting geometry have significant resistance, which is in turn heavily intertwined with their dimensions. To date, few design tools exist that couple the network layout with a resistive model for fluid channels to allow a speed up of the design cycle or expand the possibilities of fluidic circuit design. Therefore, together with collaborators from the TU Munich, we set out to develop open-source software that automatically generates chip layouts, including channel dimensions, from a given network description, fabrication constraints, and component properties.

We show how the tool was first designed and used to make a microfluidic circuit for compound testing: a passive serial diluter that creates log-scale concentration gradients and delivers them in parallel to three organ-on-chip devices. This includes designing micromixers as the functional components to create the gradients, as well as setting up a workflow that combines micromachined PMMA plates and functional PDMS chips for component and FCB fabrication. The results of characterising the mixers - together with a specification of the required flow conditions – is used as input for the tool to output standard design files.

The demonstrated approach makes it easier and more feasible to realize complex fluidic circuits in a way that we hope may accelerate microfluidics development and lower the entry barrier for researchers outside the microfluidics domain.

This presentation will discuss the progress that photonic chip technology has made over the last few years, especially for optical data communication and how silicon nitride photonic ICs are set to disrupt additional markets. Further, it will be discussed how MESA+ and local companies have collaborated to develop an ambitious plan to establish a pure-play foundry to scale up the fabrication of PICs and address a growing need in the global marketplace.