Some recent publications are listed below. A full publication list can be found here.
Recent publications
- Single-Trim Highly Accurate Frequency Reference Techniques (2025). IEEE Open Journal of the Solid-State Circuits Society (E-pub ahead of print/First online). Hoen, T. J., Delke, A. S., Jin, Y., Verlinden, J., Nauta, B. & Annema, A.-J.
- Towards Ultra Low Thermo-Mechanical Sensitive Capacitors in CMOS (2025). In 2025 IEEE European Solid-State Electronics Research Conference (ESSERC) (pp. 593-596) (Proceedings IEEE European Solid-State Electronics Research Conference (ESSERC); Vol. 2025). IEEE. Hoen, T. J., Wils, N., Verlinden, J. & Annema, A. J.
- Analysis and Design of Highly Linear Capacitive Stacking Mixer-First Receivers (2025). [Thesis › PhD Thesis - Research UT, graduation UT]. University of Twente. van Zanten, S.
- A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Ponte, J., Plompen, R., Zijlma, E., Klumperink, E. A. M., Bindra, H. S. & Nauta, B.
- A 1-8 GHz, 190MHz BB BW Mixer-First Receiver With Bootstrapped Mixer Switches Achieving Over 16dBm In-Band IIP3 (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Hardeveld, E., van der Zee, R. A. R. & Nauta, B.
- Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Rajendra, A. K., Bindra, H. S. & Nauta, B.
- A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback (2025). IEEE journal of solid-state circuits, 60(9), 3148-3163. Article 10850743. Zanten, S. v., van der Zee, R. A. R. & Nauta, B.
- Super-Vth Standard Cells With Improved EDP: Design and Silicon Validation in 65nm LP CMOS (2025). IEEE transactions on computer-aided design of integrated circuits and systems (E-pub ahead of print/First online). Yadav, S., Oude Alink, M. S. & Kokkeler, A. B. J.
- A Programmable Resolution Digital-to-Frequency or Period Converter With Sawtooth-Based Jitter Reduction (2025). IEEE journal of solid-state circuits(1558-173X). Jain, N., Klumperink, E. A. M., van Rumpt, H. & Nauta, B.
- Method of operating a load-modulated linearizer and arrangement therefor. (2025). [Patent › Patent]. Atanasov, A. N., Oude Alink, M. S. & van Vliet, F. E.
- Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption (2025). In 2025 Joint European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit): Physical Layer and Fundamentals (PHY) (pp. 643-648). IEEE. Kendae Ramkumar, V., Bindra, H. S., Klumperink, E. A. M., Abdelmagid, B. A. & Wang, H.
- A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection (2025). IEEE journal of solid-state circuits, 60(6), 1997-2012. Article 0018-9200. Kendae Ramkumar, V., Huiskamp, M., Bindra, H. S., Klumperink, E. & Nauta, B.
- Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals (2025). In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). IEEE. Rajendra, A. K., Freriksen, J. & Bindra, H. S.
- A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size (2025). IEEE journal of solid-state circuits, 60(5), 1694-1707. Article 0018-9200. Jain, N., Klumperink, E. A. M., van Rumpt, H. & Nauta, B.
- A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI (2025). In IEEE International Solid-State Circuits Conference 2025 (pp. 76-78). IEEE. Heel, J., Bindra, H. S., Louwsma, S., Dezzani, A. & Nauta, B.
- Simultaneous-multi-beam transmit arrays: A general study (2025). [Thesis › PhD Thesis - Research UT, graduation UT]. University of Twente. Atanasov, A. N.
- Analysis and Design of a Low-Loss 1–10 GHz Capacitive Stacking N-Path Filter/Mixer (2025). IEEE journal of solid-state circuits, 60(2), 367-381. Zijlma, E., van Zanten, S., Plompen, R., Klumperink, E. A. M., Nauta, B. & van der Zee, R. A. R.
- Electrical and 850 nm Optical Characterization of Back-Gate Controlled 22 nm FDSOI PIN-Diodes Without Front-Gate (2025). Journal of the Electron Devices Society, 13, 190-199. Bakker, J. H. T., Motycki, M. Ł., Hueting, R. J. E., Annema, A.-J. & Oude Alink, M.
- A 0.4–0.9 V Supply Voltage-Flexible Third-Order Passive ΔΣ Modulator With Switched-Capacitor Loop Filter Achieving 71.9 dB Peak SNDR at 4 MHz Bandwidth (2025). IEEE transactions on circuits and systems I: regular papers, 72(10), 5365-5377. Ponte, J., Nauta, B. & Bindra, H. S.
- A 12.8-GS/s Time-Interleaved Sub-Sampling ADC Front End With 38-GHz Input Bandwidth and >39-dB SNDR for 1–32 GHz in 22-nm FDSOI (2025). IEEE journal of solid-state circuits, 60(12), 4321-4335. Heel, J., Bindra, H. S., Louwsma, S. M., Dezzani, A. & Nauta, B.