Some recent publications are listed below. A full publication list can be found here.
Recent publications
- Single-Trim Highly Accurate Frequency Reference Techniques (2026). IEEE Open Journal of the Solid-State Circuits Society, 5, 481-496. Hoen, T. J., Delke, A. S., Jin, Y., Verlinden, J., Nauta, B. & Annema, A.-J.
- SSCS Student Circuit Contest: The Winners of the 2025 Edition [Society News] (2026). IEEE Solid-State Circuits Magazine, 18(1), 88-95. Alink, M. O., Zhang, Z., Yesil, E. & Marinese, D.
- Wideband Simultaneous IM2 and IM3 Cancellation in FDSOI Resistive Step RF Attenuators (2025). IEEE journal of solid-state circuits, 1-15 (E-pub ahead of print/First online). Zijlma, E., Oude Alink, M. S., Klumperink, E. A. M. & Nauta, B.
- Recent Advances in Energy-Efficient and Temperature-Resilient Sensor Interfaces (2025). IEEE Open Journal of the Solid-State Circuits Society (E-pub ahead of print/First online). Choi, W., Lee, I., Ji, Y., Delke, A., Pan, S., Tang, Z. & Chae, Y.
- Towards Ultra Low Thermo-Mechanical Sensitive Capacitors in CMOS (2025). In 2025 IEEE European Solid-State Electronics Research Conference (ESSERC) (pp. 593-596) (Proceedings IEEE European Solid-State Electronics Research Conference (ESSERC); Vol. 2025). IEEE. Hoen, T. J., Wils, N., Verlinden, J. & Annema, A. J.
- Analysis and Design of Highly Linear Capacitive Stacking Mixer-First Receivers (2025). [Thesis › PhD Thesis - Research UT, graduation UT]. University of Twente. van Zanten, S.
- A “No Gain” Direct-Conversion IQ RF-to-Bits Receiver Without Active Linear Amplification (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Ponte, J., Plompen, R., Zijlma, E., Klumperink, E. A. M., Bindra, H. S. & Nauta, B.
- A 1-8 GHz, 190MHz BB BW Mixer-First Receiver With Bootstrapped Mixer Switches Achieving Over 16dBm In-Band IIP3 (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Hardeveld, E., van der Zee, R. A. R. & Nauta, B.
- Ultra-Low-Power Dynamic-Bias Comparators With Self-Clocked Latch in 65-nm CMOS (2025). IEEE journal of solid-state circuits (E-pub ahead of print/First online). Rajendra, A. K., Bindra, H. S. & Nauta, B.
- A Capacitive Stacking Mixer-First Receiver With Higher Order Capacitive Feedback (2025). IEEE journal of solid-state circuits, 60(9), 3148-3163. Article 10850743. Zanten, S. v., van der Zee, R. A. R. & Nauta, B.
- Super-Vth Standard Cells With Improved EDP: Design and Silicon Validation in 65nm LP CMOS (2025). IEEE transactions on computer-aided design of integrated circuits and systems (E-pub ahead of print/First online). Yadav, S., Oude Alink, M. S. & Kokkeler, A. B. J.
- A Programmable Resolution Digital-to-Frequency or Period Converter With Sawtooth-Based Jitter Reduction (2025). IEEE journal of solid-state circuits(1558-173X). Jain, N., Klumperink, E. A. M., van Rumpt, H. & Nauta, B.
- Method of operating a load-modulated linearizer and arrangement therefor. (2025). [Patent › Patent]. Atanasov, A. N., Oude Alink, M. S. & van Vliet, F. E.
- Time Modulated Array and Time Variant Filter Techniques to Reduce Receiver Hardware Complexity and Power Consumption (2025). In 2025 Joint European Conference on Networks and Communications & 6G Summit (EuCNC/6G Summit): Physical Layer and Fundamentals (PHY) (pp. 643-648). IEEE. Kendae Ramkumar, V., Bindra, H. S., Klumperink, E. A. M., Abdelmagid, B. A. & Wang, H.
- A 0.5-0.8V 10-85 MS/s 12-Bit SAR ADC in 22nm FDSOI Utilizing an Inverter-Based Comparator Architecture (2025). In 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) (Symposium on VLSI Technology; Vol. 2025). IEEE. Cents, R., Bindra, H. S., De Vree, H. & Nauta, B.
- A Programmable Filtering and Frequency Translation by Aliasing IF Receiver With Alias and Harmonic Rejection (2025). IEEE journal of solid-state circuits, 60(6), 1997-2012. Article 0018-9200. Kendae Ramkumar, V., Huiskamp, M., Bindra, H. S., Klumperink, E. & Nauta, B.
- Dynamic-Window DAC Switching in SAR ADCs and its Mismatch Modelling for High Peak-to-Average Ratio Input Signals (2025). In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). IEEE. Rajendra, A. K., Freriksen, J. & Bindra, H. S.
- A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size (2025). IEEE journal of solid-state circuits, 60(5), 1694-1707. Article 0018-9200. Jain, N., Klumperink, E. A. M., van Rumpt, H. & Nauta, B.
- A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI (2025). In IEEE International Solid-State Circuits Conference 2025 (pp. 76-78). IEEE. Heel, J., Bindra, H. S., Louwsma, S., Dezzani, A. & Nauta, B.
- Simultaneous-multi-beam transmit arrays: A general study (2025). [Thesis › PhD Thesis - Research UT, graduation UT]. University of Twente. Atanasov, A. N.