Developing Heuristics for Selection of Tests for Outlier Detection in Testing of Chips
Integrated circuits are tested thoroughly in order to meet the very high demands on quality. As an additional step, outlier detection is used to detect potential unreliable chips such that quality can be improved further. However, it is often unclear to which tests outlier detection should be applied and how the parameters must be set, such that outliers are detected and yield loss remains limited.
Given a set of target devices, we can select tests for outlier detection and set the parameters for each outlier detection method using an Integer Linear Programming (ILP) approach. However, if problem sizes grow, this approach is not tractable anymore. Therefore, the goal of this project is to develop heuristics which can handle those very large optimization problems in a reasonable running time. For tractable problems, comparisons can be made to optimal solutions provided by the current ILP model.