ICT

ICT

chaired by Wilfred van der Wiel & Bram Nauta

 

14.15-14.30

The best chip is prepared for the worst

Clemens Mensink (Ansem/Cyient)

14.35-14.50

Pattern recognition using disordered networks

Bram van de Ven (NE)

14.55-15.10

Polycrystalline GaN: Materials and Devices

Gaurav Gupta (IDS)

15.15-15.30

Low input drive energy data converter design techniques

Harijot Bindra (ICD)

Abstracts

The best chip is prepared for the worst, Clemens Mensink (Ansem/Cyient)

The mission of AnSem is to put innovation on chip. This implies state-of-the-art designs to add significant value to the customer’s application. However, the customer also wants reliable chips with mature technology. How to approach this paradox? AnSem uses a well definite quality system with milestones, checklists and top-level simulations to predict the performance under all possible conditions. Managing risks is essential to ensure that brilliant ideas enhance the customer’s application. This presentation shines a light on the entire IC design process.

Pattern recognition using disordered networks, Bram van de Ven (NE)

Classification, and in particular pattern recognition, is one of the tasks where neural networks excel. By mapping linearly inseparable to linearly separable data, complex classification problems can be simplified. By studying the properties of a network of boron dopants in silicon, we found that such a network has strong nonlinearity. By exploiting this nonlinearity, it is possible to map a limited number of input data to a new, high-dimensional feature space, in which the data become linearly separable. By and using a convolutional neural network approach, it becomes possible to use our device for handwritten digit recognition. When comparing the classification accuracy obtained using the device with a computer-simulated linear classifier network, a significant increase is obtained. Our approach illustrates the power of using neuromorphic hardware for solving complex computational tasks efficiently.

Polycrystalline GaN: Materials and Devices, Gaurav Gupta (IDS)

Mono-crystalline GaN is currently a widely investigated compound semiconductor material for its interesting properties such as wide and direct bandgap, large breakdown field, suitability for high temperature and high frequency operation. It is the material of choice for high power transistor as well as optoelectronic devices such as LEDs. Despite this, its expensive production technology currently hinders its widespread commercial adaptability. In this regard, polycrystalline GaN material, which is unexploited so far, is an interesting alternative to mono-crystalline GaN for some applications as it is relatively easy and less expensive to produce. However, the polycrystalline nature of the material requires different device concepts than used in their monocrystalline counterparts. In this talk, we present our on-going experimental and TCAD investigations on polycrystalline GaN material with aim to explore novel device concept for switching as well as light emission applications.

Low input drive energy data converter design techniques, Harijot Bindra (ICD)

Analog to Digital Converters (ADCs) are crucial to capture data in almost any Internet of Everything (IoE) device as sensed physical signals have to be converted into digital data, before some processing and data transmission can take place. Today, ADCs are designed for low supply energy consumption, usually expressed in energy-per-conversion which for state-of-the art architecture is (stagnated) ~ 1fJ/conversion. However, the energy consumed from the always ON sensor interface circuitry e.g. the input driver is usually not taken into account and seldom addressed. This input drive energy (usually larger than the ADC supply energy) presents a major challenge in minimizing the energy consumption of e.g. autonomous and event-driven IoE applications. We introduce a Range Pre-selection Sampling (RPS) technique incorporated in our Successive Approximation (SA) ADC implemented in 65nm CMOS process. This RPS technique reduces the maximum voltage step at the ADCs sampling capacitors, yielding fundamentally a significant reduction in the required input charge/current/energy for the ADCs for a given analog input full-scale range. The reduced voltage step (change) at the sampling capacitors also improves the linearity of the ADC for a given full-scale range (or Signal-to-Noise ratio) in comparison to the conventional sampling technique.