PhD Defence Bruno Endres Forlin | Beyond Rad-Hard - Achieving Dependability in Constrained RISC-V Systems Through Selective Protection and Fault-Aware Design

Beyond Rad-Hard - Achieving Dependability in Constrained RISC-V Systems Through Selective Protection and Fault-Aware Design

Bruno Endres Forlin is a PhD student in the Department of Computer Architecture for Embedded Systems. (Co)Promotors are dr.ir. M. Ottavi and dr.ir. N. Alachiotis from the Faculty of Electrical Engineering, Mathematics and Computer Science.

This thesis investigates dependable execution on resource-constrained RISC-V systems without relying on radiation-hardened hardware or full-featured operating systems. Motivated by the increasing use of Commercial Off-The-Shelf (COTS) microcontroller-class platforms in safety- and mission-critical edge deployments, the work addresses two challenges: limited design-centric methods for evaluating radiation-induced faults, and the lack of lightweight mechanisms for fault containment in deeply embedded software stacks.

The thesis establishes an empirical basis by characterizing unprotected RISC-V systems under radiation. Neutron and proton beam experiments are conducted on SRAM-based and Flash-based FPGA implementations of RISC-V soft cores. Fault propagation is analyzed from low-level upsets to system-level failures, showing that mutable memories dominate system vulnerability, while reconfigurable logic introduces additional failure modes. These results motivate selective, structure-aware protection rather than uniform redundancy.

Building on this foundation, this work presents a test-driven methodology for radiation evaluation of heterogeneous RISC-V designs. The methodology separates the device under test, test fixture, and monitoring infrastructure, enabling reproducible experiments and clearer attribution of observed failures. In addition, a low-overhead software instrumentation framework based on RISC-V performance counters provides execution-level observability with bounded runtime and memory overhead.

Overall, this work shows that dependable RISC-V systems can be achieved through empirical fault characterization, selective protection, and fault-aware software–hardware co-design suited to embedded edge platforms.