Dynamic effects in silicon power MOSFETs
Riccardo Tambone is a PhD student in the department Power Electronics. (Co)Promotors are dr.ir. R.J.E. Hueting and dr. A. Ferrara from the Faculty of Electrical Engineering , Mathematics and Computer Science (EEMCS), University of Twente.
As climate change challenges grow, the energy transition and efficient energy management have become critical factors in reducing greenhouse gas emissions. In this context, optimising the performance of power semiconductor devices is fundamental. These devices play a crucial role in the conversion and management of electrical energy, important for the energy transition, as well as in handling the continuously increasing electric power consumption required for modern life (such as portable electronics, data centres, electric vehicles, robotics and more).
Power semiconductor devices are the key elements of power converters, i.e., the electrical circuits that manage and convert electrical energy. In these converters, the devices act as switches, either blocking current or allowing it to flow.
The power electronics industry has consistently been driven by the need for more efficient, smaller circuits capable of handling higher power, i.e., higher power density. This trend allows for reduced costs and opens up new market and application opportunities. A simple solution for higher power density is to increase the switching frequency of the power devices, which allows other circuit components to be reduced in size. However, increasing the switching frequency can negatively impact converter efficiency. In particular, it subjects power semiconductor devices to high electrical stress, which increases their losses because of dynamic effects.
A widely used power semiconductor device in a wide range of applications is the power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). This thesis investigates the mechanisms that play a role during fast switching of a special class of silicon (Si) power MOSFETs, i.e., the split-gate trench (SGT) MOSFET. Owing to their complex design, these devices contain parasitic elements (resistances and capacitances) that interact strongly at high switching speeds. These interactions introduce delays and consequently lead to different conditions in different parts of the device (i.e., distributed effects), resulting in current crowding. In addition, an internal parasitic (i.e., body) diode is inherently present. This often affects the switching behaviour of the power MOSFET as well, causing more switching delays (reverse recovery) and oscillations. These phenomena increase the power losses and affect the device robustness.
After a thorough literature review to understand the major criticality of power MOSFETs, their dynamic behaviour is measured, simulated and modelled. New dedicated test structures for the transmission line pulse (TLP) setup have been developed in order to characterise the device parasitics, to analyse the distributed effects, and their impact on the current sharing inside the device. The device physics in those conditions has been studied by adopting carefully calibrated technology computer aided design (TCAD), i.e. commercial finite element method, device simulations. The comparison between such simulations and measurements allows us to understand what happens inside the device for different operating conditions.
Two new physics-based models have been developed to simulate the MOSFET behaviour in circuit simulation tools. The first model describes the breakdown voltage evolution depending on the field plate (FP) potential and current density. The second model describes the reverse recovery of the power MOSFET including that with a linearly graded doping.
This work allows to understand the importance of an optimised device design in minimising the unwanted dynamic behaviour of the power MOSFET. In addition, it reveals how the interaction between the device current and gate and FP potentials leads to a different current distribution than expected. Finally, it presents an accurate model of the reverse recovery mechanism inside power MOSFETs, that can be used for analysing the impact of both the injected charge (diffusion charge) and the output capacitance (depletion capacitance) on the switching behaviour. This model can be applied to different kinds of devices, such as conventional and superjunction trench MOSFETs, pin diodes, and silicon carbide (SiC) devices.
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