Reconfigurable Computing (RC) examines the potential of FPGAs for realizing dynamically reconfigurable (adaptive) systems as well as the aspects of reliability, security, and efficiency of future nanoelectronic designs.
Reconfigurable hardware systems are able to implement a desired circuit structure according a given configuration. The research field of architectures of such reconfigurable hardware systems as well as algorithms and applications involving reconfigurable hardware systems is called Reconfigurable Computing.
The mainly used reconfigurable devices are Field Programmable Gate Arrays (FPGAs) which belong to the family of PLDs (Programmable Logic Devices). FPGAs are digital chips that can be programmed for implementing arbitrary digital circuits. This means that FPGAs have first to be programmed with a so called configuration (often called a configuration bitstream) to set the desired behavior of the used functional elements of the FPGA. FPGAs have a significant market segment in the microelectronics and, particularly in the embedded system area.
Dynamic reconfiguration of FPGAs is the exchange of the FPGA configuration during runtime. Partial dynamic reconfiguration means that parts of the configuration can be exchanged during runtime, whereas the remainder of the configuration stays active. Dynamic and especially partial reconfiguration needs additional hardware support of the configuration manager of the FPGA.
Partial reconfiguration is physically supported in FPGAs since many years. However, the usage for industrial designs is still in its infancy and not yet exploring the great opportunities which might be offered by partial dynamic reconfiguration.
FPGA support for partial reconfiguration is the precondition for utilizing partial reconfiguration. However, a corresponding design flow in order to build such a system is also needed. A partial reconfigurable design is usually split into two parts: The a) static part is always present and only configured at power up of the system. In this part, usually the interfaces to peripheral devices, memory controllers, and the access to the configuration interface of the FPGA (e.g., the ICAP for Xilinx FPGAs) is included. The configuration of one or several b) partial reconfigurable parts or areas can be exchanged during runtime.
These areas are usually embedded and surrounded by the static part. In these partial reconfigurable areas, modules and operations are implemented which can be adapted or exchanged during runtime.
By utilizing partial dynamic reconfiguration, flexible adaptive digital circuits can be realized. These adaptive digital circuits are able to modify their structure at run time in order to cope with environment or requirement changes as well as different user requests. By utilizing this technique, a high degree of flexibility can be reached which leads to energy efficient and high performance implementations. On the other hand, these kinds of circuits are able to be resistant to harsh environment conditions by quick reacting on environment changes through structure adaption. This behavior leads to more reliable system, if, for example, the reconfigurable system can adapt to certain radiation levels. Furthermore, the security of FPGA-based implementation against physical attacks, like side-channel analysis, fault injection attacks, or reverse engineering, can be enormously increased.
Dr.-Ing. habil. Daniel Ziener