PhD Defence Ranasinghe Wijesundara Ranasinghe Appuhamilage| CMOS Transistor-Topology Engineering for Minimal-Energy Near-Threshold Computing | Exploring Alternative Logic Styles for Low-Energy IoT Devices

CMOS Transistor-Topology Engineering for Minimal-Energy Near-Threshold Computing | Exploring Alternative Logic Styles for Low-Energy IoT Devices

Ranasinghe Wijesundara Ranasinghe Appuhamilage is a PhD student in the department Computer Architecture Design and Test for Embedded Systems. (Co)Promotors are prof.dr.ir. M.J.G. Bekooij and dr.ir. S.H. Gerez from the faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), University of Twente.

The necessity of Energy Autonomous Devices (EAD) has recently emerged in wireless consumer electronics owing to their escalating performance demands. Most of these devices require higher performance at extremely low energy consumption. For instance, an EAD might process a highly computationally intensive algorithm (i.e. Deep/Convolution Neural Network) within a very short period of time. The embedded micro-controller of the EAD is responsible for this task. Although the rapid evolution of semiconductor technologies satisfies this performance need, operating the end devices for a reasonable energy budget has become a daunting task. The portable, batterypowered, and ubiquitous Internet of Things (IoT) vigorously rely on the lifetime of the energy source and therefore, energy efficiency has become the primary design goal in their recent implementation. As the name implies, EAD is a device that sustains as long as possible under known or unknown environmental conditions, processing the information without being connected to the energy grid. A wireless transponder that can be mounted on vehicles is a prime example for an EAD, which informs the presence of the aggressive vehicles to the vulnerable road-users (children, disabled people, etc.) next to them. The EADs are heterogeneous by their nature; meaning, a single unit is composed of a processor, communication blocks, a radio system and power management. Therefore the energy efficiency can be exploited beyond the focal processing block, leading to energy savings in multiple abstraction levels. However, this potential strongly depends on the nature of the application of interest and might limit this gain for general-purpose end-use. i.e. A general-purpose micro-controller cannot be used energy efficiently for many different applications. EADs are in dire need of application-independent strategies to achieve a reasonable performance against their stringent energy budget. Hence this inevitably limits the energy-saving possibility to the lowest level of abstraction of the design space, the digital CMOS circuits or in other words, MOSFET transistors. Since there is no notion of the application context at this transistor level, any energy efficient solution provided within this scope is application independent. Such miniaturized CMOS circuits ( m/nm level) that can be used for electronic design automation are 𝜇 called standard cells. In the industry, they are usually available as commercial IP packages. However, a tailored version for ultra-low-energy operation too can be introduced with our own engineering effort. The best analogy that can be given related to this context is a bridge that was constructed using LEGO blocks. Instead of using the existing ones, we envision for a smart solution by making these LEGO blocks light weight, without compromising their strength. Therefore, the bridge constructed from these new blocks is as strong as the older one, but lighter! On top of that, these LEGO blocks can be used to design bridges in many different shapes, without being worried about their application use. Similarly, we envision an energy-efficient standard cell library with custom, tailored cell templates without compromising their performance. We have re-engineered the transistor arrangement in each cell to make them more compact, energy efficient, preserving the robustness of operation. This is analogous to tweaking the individual LEGO blocks for their light weight use. The reduction of the supply voltage has a quadratic effect on the power consumption of these circuits at the expense of lower operating speed. The voltage at which the least energy is consumed is typically referred as the Minimum Energy Point (MEP) which is often located closer to the threshold voltage of the transistor (VTH). This is called the near-VTH operating region. Operating the transistors, and EADs closer to the MEP poses several challenges, including susceptibility for the so-called Process, Voltage and Temperature (PVT) variations of the circuits. And these impacts are reflected in the degradation of robustness, noise margin, and glitch/noise immunity of individual cells. Hence further pushing this MEP boundary in the designer's favor is even more challenging. This thesis addresses the challenges mentioned above in achieving a lower MEP from the transistor level up to the macro-blocks (i.e. ALUs, Hardware Accelerators, FPGAs etc). At the circuit level, several topological engineering steps take place to improve the standard cell speed and robustness at ultra-low-voltage levels enhancing the noise margin, PVT immunity, and glitch immunity of these cells. This means, the standard cell templates are modified according to a specific set of steps, re-engineering their transistor arrangement. At higher design levels, these circuits are effectively used to implement large-scale, complex digital circuits (i.e. RISC-V core). This work efficiently uses these standard cells in large-scale designs by improving the near-VTH cell characterization accuracy and augmenting conventional VLSI design flow. Utilizing the proposed strategies, we have demonstrated up to 30%-60% energy savings for cell/macro-level implementations. This is indeed without compromising the other vital circuit parameters as stated above. In this way, multiple challenges in the context of near-VTH computing have been overcome, thereby advancing in the field of ultra-low energy digital systems and variation-resilient digital designs.