Summary Marko Sturm

This thesis describes research on the growth of thin oxide films on silicon substrates for use as gate dielectric in microelectronics. The aggressive scaling of metal-oxide-semiconductor field-effect transistor (MOSFET) based microelectronics has led to a large increase of the computing power of integrated circuits, but further downscaling of the gate dielectric will lead to problems due to excessive leakage current between gate and channel. The introduction of high dielectric permittivity – so-called high-K – oxides as replacement for SiO₂ is suggested in order to achieve the required gate-channel capacitance with a thicker oxide film and lower leakage current. Introduction of high-K oxides in the Complementary Metal-Oxide-Semiconductor (CMOS) process flow is a large change. Instead of SiO₂ growth by thermal oxidation of the silicon substrate, a high-K dielectric will have to be deposited and also the subsequent processing steps for device fabrication are more complicated with a high-K dielectric. The Si/SiO₂ interface is known for its good electrical properties and the growth conditions for high-K deposition will have to be carefully chosen in order to give an equivalent performance. Among various deposition techniques that have been suggested for growth of high-K dielectrics, Atomic Layer Deposition (ALD) has attracted considerable interest. Since ALD relies on self-limiting gas-surface reactions, the controllability of the film thickness, composition and stoichiometry is relatively easy compared to other methods for thin film deposition. For large area deposition, the homogeneity of the thickness of the deposited film is probably unsurpassed.

The interface between the silicon substrate and the gate dielectric plays an important role for the performance of MOSFETs. Furthermore, the mechanisms of interface formation are completely different for thermal oxide growth and ALD. These reasons make it increasingly more important to perform in-situ analysis of gate dielectrics, without vacuum break between deposition and analysis. Ex-situ analysis of the oxide layer and its interface with the substrate is only possible if the sample is sufficiently stable upon air exposure. This typically requires an oxide thickness of a few nanometre, which generally hinders a sensitive analysis of the interface.

The reduction of lateral sizes in integrated circuit fabrication makes nanometre scale analysis of gate dielectrics more important. Atomic Force Microscopy (AFM) is now a well-established method to investigate the surface morphology of conducting and insulating samples with high resolution. The use of a conducting tip gives the possibility to probe also electrical characteristics of the sample under investigation, usually in combination with a topographical measurement.

The work described in this thesis has been performed with a unique ultra-high vacuum (UHV) deposition and analysis set-up. In this set-up aluminium oxide (Al₂O₃) can be deposited by ALD from trimethylaluminium (TMA) and water vapour. The part of the system for sample analysis is assembled from a commercially available X-ray Photoelectron Spectroscopy set-up and a UHV beam-deflection AFM. Samples can be transferred between the ALD reactor and the analysis system via a connection chamber.

Most results have been obtained from combined measurements of topography and detection of electrostatic forces in non-contact frequency modulation AFM by voltage-dependent spectroscopy and lock-in techniques, i.e. Kelvin Probe Force Microscopy (KPFM). Due to the absence of water condensation on the sample in UHV and the high sensitivity of the frequency modulation technique this allows highly sensitive measurements of electrostatic forces.

Chapter 4 shows how non-contact AFM can be used to probe localised charges in Al₂O₃ films. The polarity of such charges can be determined by bias-dependent imaging and KPFM measurements, revealing that these charges are mostly negative. The physical background of the bias-dependent contrast of a charge in AFM images can be understood with image charge models. By measuring the distribution of the electrostatic interactions on different oxide charges within one sample it was shown that the depth distribution of these charges is homogeneous.

Besides large local variations due to localised charges, oxide films on silicon also show smaller lateral variations in electrostatic force due to inhomogeneities in the Contact Potential Difference (CPD) and capacitance. Lateral variations in CPD can be related to states at the interface between the oxide and the silicon substrate, whereas capacitance inhomogeneities are related to in variations the oxide thickness. These inhomogeneities, more commonly called fluctuations, are investigated in chapter 5. KPFM measurements on samples with different doping density of the substrate and at different sample temperature indicate that dipoles at the silicon/oxide interface or across the oxide layer are the most probable cause of CPD fluctuations.

By comparing Al₂O₃ films deposited on different starting surfaces, we showed that the nucleation of the ALD process has a pronounced influence on these fluctuations and their correlation with the topography of the sample surface, especially for the homogeneity of the capacitance. This stresses the importance of the silicon/oxide interface for the electrical properties of the gate dielectric.

The observation that the initial nucleation of the oxide is so important for the electrical homogeneity of the final layer brought us to the initial oxidation experiments of the next three chapters. The room-temperature oxidation of Si(111) 7´7, described in chapter 6, is not directly relevant for CMOS technology (which uses (001) oriented surfaces) but appeared to be very helpful in identifying the processes that occur upon oxidation of a clean silicon surface. This made it much easier to interpret the more difficult to understand results of the oxidation of Si(001).

Although numerous studies on the oxidation of Si(111) have been published in literature, we could still learn new things from laterally resolved contact potential difference measurements. The most important conclusion is that the work function map of a clean Si(111) sample is essentially flat and that CPD fluctuations develop within the formation of a monolayer of silicon oxide. The pattern of the CPD image is subject to large changes in the initial stage of the oxidation due to formation of Si-O bonding at the interface and the influence of the metastable Höfer precursor on the work function. After a monolayer has been formed the CPD still changes, because through oxidation changes the bonding at the silicon/oxide interface. This indicates that the measurement of the CPD is sensitive to the silicon/oxide interface. Oxidation of silicon (111) at room temperature appears to be a heterogeneous process, without preference for step edges.

Initial oxidation of clean Si(001) 2´1, described in chapter 7, shows to be rather complex when compared to Si(111). Continuous and non-continuous oxidation experiments at room temperature and low temperature were needed to understand the oxidation processes on this surface. At least two chemisorption processes are coexisting for oxidation of the clean surface by molecular oxygen. One process we could identify is characterised by a fast dissociation of the oxygen molecule after chemisorption, leading to a decrease of the work function. A second process involves a metastable precursor state before the oxygen is incorporated in a stable position in the silicon lattice. We could clearly identify this state at room temperature, at low temperature it is even more pronounced.

Chapter 8 again deals with oxidation of Si(001) but moves from UHV prepared samples to wet-chemically prepared HF dipped samples that are directly relevant for device fabrication. Under typical manufacturable processing conditions in an ALD reactor an interfacial SiO₂ layer growth between the silicon substrate and the high-K oxide as a result of the reaction of the substrate with oxygen contamination of the purge gas. By monitoring the changes in topography and CPD during oxygen exposure at typical processing temperatures for ALD growth, it was shown that the nature of this oxidation process differs from the initial oxidation of clean surfaces at room temperature. Active oxidation processes lead to etching of surface features, resulting in a flattening of the topography. The flattening of the surface is however not accompanied by a decrease in the CPD fluctuations, indicating that the electrical quality of the Si/oxide interface is not improved. The initial magnitude of the CPD fluctuations on the hydrogen-terminated surface is already equal to that of the oxidised surface and higher compared to the fluctuation level on the oxidised UHV prepared Si(001) surface. This indicates that the quality of the wet-chemical pre-treatment is decisive for the final interface quality.

This thesis combines rather applied work on the properties of ALD grown films with more fundamental research on the oxidation of clean silicon surfaces. By making this combination this kind of work can give a better understanding of processes involved in deposition of gate dielectrics on the one hand and a contribution to classical surface science on the other hand.

The results of chapter 8 indicate that good surface pre-treatment is essential in order to obtain a good interface quality. The standard pre-treatment based on wet-chemical hydrogen termination as final cleaning step introduces substantial fluctuations in CPD. In-situ substrate pre-treatment before gate dielectric deposition will probably be required in the future, certainly when moving to epitaxial dielectrics. In this thesis we showed how KPFM can be directly applied after the pre-treatment and how the formation of an ultra-thin oxide layer can be investigated under controlled conditions. It is definitely interesting to continue research in this direction.

High-K is definitely not the only step in improvement of CMOS device performance. Actually, other ways to improve device performance, such as mobility enhancement by using a strained silicon channel for improved electron mobility or metal gates for elimination of poly-Si depletion are now regarded as better candidates for short-term integration in the CMOS process, such that the introduction of high-K can be slightly delayed. The introduction of these new materials and methods in nanometre scale devices offers further opportunities for application of laterally resolved electrical analysis methods.

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Home News Events Strategic Orientations research groups Publications PhD students Education MESA+ NanoLab Starting entrepreneurs Tech Park Industrial Partners Vacancies Links Sitemap Search	Summary Marko Sturm This thesis describes research on the growth of thin oxide films on silicon substrates for use as gate dielectric in microelectronics. The aggressive scaling of metal-oxide-semiconductor field-effect transistor (MOSFET) based microelectronics has led to a large increase of the computing power of integrated circuits, but further downscaling of the gate dielectric will lead to problems due to excessive leakage current between gate and channel. The introduction of high dielectric permittivity – so-called high-K – oxides as replacement for SiO₂ is suggested in order to achieve the required gate-channel capacitance with a thicker oxide film and lower leakage current. Introduction of high-K oxides in the Complementary Metal-Oxide-Semiconductor (CMOS) process flow is a large change. Instead of SiO₂ growth by thermal oxidation of the silicon substrate, a high-K dielectric will have to be deposited and also the subsequent processing steps for device fabrication are more complicated with a high-K dielectric. The Si/SiO₂ interface is known for its good electrical properties and the growth conditions for high-K deposition will have to be carefully chosen in order to give an equivalent performance. Among various deposition techniques that have been suggested for growth of high-K dielectrics, Atomic Layer Deposition (ALD) has attracted considerable interest. Since ALD relies on self-limiting gas-surface reactions, the controllability of the film thickness, composition and stoichiometry is relatively easy compared to other methods for thin film deposition. For large area deposition, the homogeneity of the thickness of the deposited film is probably unsurpassed. The interface between the silicon substrate and the gate dielectric plays an important role for the performance of MOSFETs. Furthermore, the mechanisms of interface formation are completely different for thermal oxide growth and ALD. These reasons make it increasingly more important to perform in-situ analysis of gate dielectrics, without vacuum break between deposition and analysis. Ex-situ analysis of the oxide layer and its interface with the substrate is only possible if the sample is sufficiently stable upon air exposure. This typically requires an oxide thickness of a few nanometre, which generally hinders a sensitive analysis of the interface. The reduction of lateral sizes in integrated circuit fabrication makes nanometre scale analysis of gate dielectrics more important. Atomic Force Microscopy (AFM) is now a well-established method to investigate the surface morphology of conducting and insulating samples with high resolution. The use of a conducting tip gives the possibility to probe also electrical characteristics of the sample under investigation, usually in combination with a topographical measurement. The work described in this thesis has been performed with a unique ultra-high vacuum (UHV) deposition and analysis set-up. In this set-up aluminium oxide (Al₂O₃) can be deposited by ALD from trimethylaluminium (TMA) and water vapour. The part of the system for sample analysis is assembled from a commercially available X-ray Photoelectron Spectroscopy set-up and a UHV beam-deflection AFM. Samples can be transferred between the ALD reactor and the analysis system via a connection chamber. Most results have been obtained from combined measurements of topography and detection of electrostatic forces in non-contact frequency modulation AFM by voltage-dependent spectroscopy and lock-in techniques, i.e. Kelvin Probe Force Microscopy (KPFM). Due to the absence of water condensation on the sample in UHV and the high sensitivity of the frequency modulation technique this allows highly sensitive measurements of electrostatic forces. Chapter 4 shows how non-contact AFM can be used to probe localised charges in Al₂O₃ films. The polarity of such charges can be determined by bias-dependent imaging and KPFM measurements, revealing that these charges are mostly negative. The physical background of the bias-dependent contrast of a charge in AFM images can be understood with image charge models. By measuring the distribution of the electrostatic interactions on different oxide charges within one sample it was shown that the depth distribution of these charges is homogeneous. Besides large local variations due to localised charges, oxide films on silicon also show smaller lateral variations in electrostatic force due to inhomogeneities in the Contact Potential Difference (CPD) and capacitance. Lateral variations in CPD can be related to states at the interface between the oxide and the silicon substrate, whereas capacitance inhomogeneities are related to in variations the oxide thickness. These inhomogeneities, more commonly called fluctuations, are investigated in chapter 5. KPFM measurements on samples with different doping density of the substrate and at different sample temperature indicate that dipoles at the silicon/oxide interface or across the oxide layer are the most probable cause of CPD fluctuations. By comparing Al₂O₃ films deposited on different starting surfaces, we showed that the nucleation of the ALD process has a pronounced influence on these fluctuations and their correlation with the topography of the sample surface, especially for the homogeneity of the capacitance. This stresses the importance of the silicon/oxide interface for the electrical properties of the gate dielectric. The observation that the initial nucleation of the oxide is so important for the electrical homogeneity of the final layer brought us to the initial oxidation experiments of the next three chapters. The room-temperature oxidation of Si(111) 7´7, described in chapter 6, is not directly relevant for CMOS technology (which uses (001) oriented surfaces) but appeared to be very helpful in identifying the processes that occur upon oxidation of a clean silicon surface. This made it much easier to interpret the more difficult to understand results of the oxidation of Si(001). Although numerous studies on the oxidation of Si(111) have been published in literature, we could still learn new things from laterally resolved contact potential difference measurements. The most important conclusion is that the work function map of a clean Si(111) sample is essentially flat and that CPD fluctuations develop within the formation of a monolayer of silicon oxide. The pattern of the CPD image is subject to large changes in the initial stage of the oxidation due to formation of Si-O bonding at the interface and the influence of the metastable Höfer precursor on the work function. After a monolayer has been formed the CPD still changes, because through oxidation changes the bonding at the silicon/oxide interface. This indicates that the measurement of the CPD is sensitive to the silicon/oxide interface. Oxidation of silicon (111) at room temperature appears to be a heterogeneous process, without preference for step edges. Initial oxidation of clean Si(001) 2´1, described in chapter 7, shows to be rather complex when compared to Si(111). Continuous and non-continuous oxidation experiments at room temperature and low temperature were needed to understand the oxidation processes on this surface. At least two chemisorption processes are coexisting for oxidation of the clean surface by molecular oxygen. One process we could identify is characterised by a fast dissociation of the oxygen molecule after chemisorption, leading to a decrease of the work function. A second process involves a metastable precursor state before the oxygen is incorporated in a stable position in the silicon lattice. We could clearly identify this state at room temperature, at low temperature it is even more pronounced. Chapter 8 again deals with oxidation of Si(001) but moves from UHV prepared samples to wet-chemically prepared HF dipped samples that are directly relevant for device fabrication. Under typical manufacturable processing conditions in an ALD reactor an interfacial SiO₂ layer growth between the silicon substrate and the high-K oxide as a result of the reaction of the substrate with oxygen contamination of the purge gas. By monitoring the changes in topography and CPD during oxygen exposure at typical processing temperatures for ALD growth, it was shown that the nature of this oxidation process differs from the initial oxidation of clean surfaces at room temperature. Active oxidation processes lead to etching of surface features, resulting in a flattening of the topography. The flattening of the surface is however not accompanied by a decrease in the CPD fluctuations, indicating that the electrical quality of the Si/oxide interface is not improved. The initial magnitude of the CPD fluctuations on the hydrogen-terminated surface is already equal to that of the oxidised surface and higher compared to the fluctuation level on the oxidised UHV prepared Si(001) surface. This indicates that the quality of the wet-chemical pre-treatment is decisive for the final interface quality. This thesis combines rather applied work on the properties of ALD grown films with more fundamental research on the oxidation of clean silicon surfaces. By making this combination this kind of work can give a better understanding of processes involved in deposition of gate dielectrics on the one hand and a contribution to classical surface science on the other hand. The results of chapter 8 indicate that good surface pre-treatment is essential in order to obtain a good interface quality. The standard pre-treatment based on wet-chemical hydrogen termination as final cleaning step introduces substantial fluctuations in CPD. In-situ substrate pre-treatment before gate dielectric deposition will probably be required in the future, certainly when moving to epitaxial dielectrics. In this thesis we showed how KPFM can be directly applied after the pre-treatment and how the formation of an ultra-thin oxide layer can be investigated under controlled conditions. It is definitely interesting to continue research in this direction. High-K is definitely not the only step in improvement of CMOS device performance. Actually, other ways to improve device performance, such as mobility enhancement by using a strained silicon channel for improved electron mobility or metal gates for elimination of poly-Si depletion are now regarded as better candidates for short-term integration in the CMOS process, such that the introduction of high-K can be slightly delayed. The introduction of these new materials and methods in nanometre scale devices offers further opportunities for application of laterally resolved electrical analysis methods.