Jelena Marinčić

Systematic Verification of Embedded Systems

Description of research

There are many languages and tools for embedded systems verification. However, one is often left without methods how to use them.

Verification means that a model of the system (the embedded software and its physical environment) is designed and requirements are formalised. The software part of a system can, in principle, be modelled automatically, but the physical part of the system must be modelled manually and informally.

Our goal is to provide a modelling method that:

- makes the modelling process repeatable and less dependent on a modeller

- enhances the quality of an informal argument that the model accurately represents the system

- enhances the quality of the model.

We have been testing and improving the method by doing several case studies.

Advisors

Prof. Dr. Roel Wieringa

Dr. Angelika Mader

Duration

2005 - 2009

Project

MOCA – Modelling Control Aspects of Embedded Systems