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Dependable Heterogeneous Design at Circuit Level
Description of research
The project's aim is to design dependable heterogeneous circuits, which include digital resources, analog-digital and digital-analog circuits and sensors.
Nowadays, in heterogeneous systems, the testing of analogue circuits determine the majority of diagnosis and repair problems and costs. In safety-critical and heavy environmental condition applications, like electronics in medical and automotive applications, the dependability of these circuits is of key importance.
Basic idea is to implement a high dependability of heterogeneous systems by developing both Built-In Self-Diagnostics (BISD) as well as Built-In Self-Repair (BISR) circuits using a combination of hardware and software, with a focus on sensor IP (sensor + associated MS circuits).
In addition, transistor aging effect, like NBTI in nano-scaled CMOS technology become essential.
So the project also check the aging based statistic influence on analog-front-end (AFE) circuits. And to provide a AFE which is insensitive to the aging and process variation in circuit level.
The planned activities are as follows:
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Study the NBTI effect on 65nm CMOS and check the influence on different IPs in AFE |
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Modelling at low level of sensor IP and development of potential repair structures or circuits |
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The design and fault simulation of the dependable IP circuitries |
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Circuit verification of the dependable heterogeneous circuits |
Advisor(s)
dr. ir. Hans Kerkhoff
prof. dr. ir. Gerard Smit
Duration
2010-2014
Project
TOETS -- Towards One European Test Solution
Funding institution
CATRENE is the successor of MEDEA+ in which MS have allocated 129.5 M€ funding allocated to projects running in 2007 mainly coming from France (62), the Netherlands (30), and Germany (26) with smaller contributions from Belgium/Flanders (6.5), Spain (3), Austria (1) and Sweden (1).
Strategic Research Orientation
Links to relevant web pages:
http://caes.ewi.utwente.nl/people/caes-members/phd-students/42-jinbo-wan
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